Advanced Programmable Interrupt Controller; Apic Configuration - Intel MultiProcessor Specification

only during the initialization and shutdown processes. The BSP is responsible for initializing the
system and for booting the operating system; APs are activated only after the operating system is
up and running. CPU1 is designated as the BSP. CPU2, CPU3, and so on, are designated as the
APs.
INTERRUPT
REQUESTS
2.1.2

Advanced Programmable Interrupt Controller

The Advanced Programmable Interrupt Controller (APIC) is based on a distributed architecture in
which interrupt control functions are distributed between two basic functional units, the local unit
and the I/O unit. The local and I/O units communicate through a bus called the Interrupt Controller
Communications (ICC) bus, as shown in Figure 2-2.
In a multiprocessor system, multiple local and I/O APIC units operate together as a single entity,
communicating with one another over the ICC bus. The APIC units are collectively responsible
for delivering interrupts from interrupt sources to interrupt destinations throughout the
multiprocessor system.
The APICs help achieve the goal of scalability by doing the following:
Off-loading interrupt-related traffic from the memory bus, making the memory bus more
available for processor use.
Helping processors share the interrupt processing load with other processors.
The APICs help achieve the goal of AT-compatibility by cooperating with 8259A-equivalent PICs
in the system.
Version 1.4
BSP AP1
CPU 1 CPU 2
LOCAL LOCAL
APIC APIC
1 2
ICC BUS
0
1
2
3
4
5
6
I/O
7
8
APIC
9
10
11
12
13
14
15
Figure 2-2. APIC Configuration
AP2
CPU 3
LOCAL
APIC
3
0
1
2
3
4
5
INTERRUPT 6
I/O
7
REQUESTS
APIC
8
9
10
11
12
13
14
15
System Overview
2-3