Compatibility Bus Address Space Modifier Entries; Bus Hierarchy Descriptor Entry Fields - Intel MultiProcessor Specification

MultiProcessor Specification
Table 4-15 Bus Hierarchy Descriptor Entry Fields
Field
ENTRY TYPE
ENTRY LENGTH
BUS ID
BUS INFORMATION:SD
PARENT BUS
For buses where the BUS INFORMATION:SD bit is set, System Address Mappings may not be
needed. Since the bus is defined as being subtractive decode, the range of addresses that appear on
the bus can be derived from address decoding information for parent and peer buses.
4.4.3 Compatibility Bus Address Space Modifier Entry
The Compatibility Bus Address Space Modifier defines a set of predefined address ranges that
should either be added or removed from the supported address map ranges for a given bus. This
entry type is used in combination with System Address Space Mapping entries to complete the
description of memory and I/O ranges that are visible on a bus that incorporates support for ISA
device compatibility.
4-22
Offset Length
(in bytes:bits) (in bits)
0 8
1 8
2 8
3:0 1
4 8
Description
Entry type 129 identifies a Bus Hierarchy
Descriptor Entry.
A value of 8 indicates that this entry type is eight
bytes long.
The BUS ID identity of this bus. This number
corresponds to the BUS ID as defined in the
base table bus entry for this bus.
Subtractive Decode Bus. If set, all addresses
visible on the parent bus but not claimed by
another device on the parent bus (including
bridges to other buses) are useable on this bus.
Parent Bus. This number corresponds to the
BUS ID as defined in the base table bus entry for
the parent bus of this bus
Version 1.4