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Intel MultiProcessor Specification page 68

Intel multiprocessor specification
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MultiProcessor Specification
The 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes
INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs,
which makes NMI dynamically routable via software.
In PIC-Mode configurations, the NMI signal is delivered to the local interrupt input 1 (LINTIN1)
of all local APICs and the input of a 2-to-1 MUX. When the system is operated in PIC Mode, the
NMI is sent to the BSP directly via the MUX. The BIOS and the operating system must leave the
LINTIN1 of all local APICs disabled to ensure that the BSP is the only processor that receives the
NMI.
In PIC-Mode configurations, the 8259 INTR signal also follows the same convention, connecting
to the local interrupt line 0 (LINTIN0) of all local APICs and the input of the second 2-to-1 MUX.
When the system is operated in PIC Mode, the 8259 INTR is sent to the BSP directly via the
MUX. The BIOS and the operating system must leave the LINTIN0 of all local APICs disabled to
ensure that the BSP is the only processor that receives the 8259 INTR signal.
When the system is operated in Symmetric I/O Mode, the operating system may enable the
LINTIN0 and LINTIN1 of any or all local APICs as necessary.
5-8
Version 1.4

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