Systems developers must assign APIC local unit IDs and ensure that all are unique. There are two
acceptable ways to assign local APIC IDs, as follows:
By hardware. The ID of each APIC local unit is sampled from the appropriate pins at RESET.
By the BIOS. Software can override the APIC IDs assigned by hardware by writing to the
Local Unit ID Register. This is possible only with help from the hardware; for example, using
board ID registers that the software can read to determine which board has the BSP.
Local APIC IDs must be
The MP operating system can use the local APIC ID to determine on which processor it is
The ID of each I/O APIC unit is set to zero during RESET. It is the responsibility of the operating
system to verify the uniqueness of the I/O APIC ID and to assign a unique ID if a conflict is found.
The assignment of APIC IDs for I/O units must always begin from the lowest number that is
possible after the assignment of local APIC IDs. The operating system must not attempt to change
the ID of an APIC I/O unit if the preset ID number is acceptable.
APIC Interval Timers
The 82489DX APIC local unit contains a 32-bit wide programmable timer with the following two
independent clock input sources:
1. The CLK pin provides the clock signal that drives the 82489DX APIC's internal operation.
2. The TMBASE pin allows an independent clock signal to be connected to the 82489DX APIC
for use by the timer functions.
The interval timers of the integrated APIC have only one clock input source, CLK. To maintain
consistency, developers of compliant systems based on the 82489DX must choose CLK as the
source of the 82489DX APIC timer clock. TMBASE must be left disabled. An MP operating
system may use the IRQ8 real-time clock as a reference to determine the actual APIC timer clock
Special consideration must be made for systems with stop clock (STPCLK#) capability. Timer
interrupts are ignored while STPCLK# is asserted. The system time-of-day clock may need to be
reset when STPCLK# is deasserted.
Multiple I/O APIC Configurations
Systems may provide more than one I/O APIC for increased interrupt scalability in Symmetric I/O
Mode. To preserve PC/AT compatibility in PIC or Virtual Wire mode, interrupts connected to
additional I/O APICs must also be connected to the 8259A
Figure 3-6 represents one possible interrupt
associated I/O APIC. To prevent non-ISA interrupts from appearing at inputs on both I/O APICs,
the hardware must provide a means to disable the interrupt routing network when the system
switches to symmetric I/O mode with the second I/O APIC enabled.
More information about the implementation of multiple I/O APIC configurations is presented in
need not be consecutive.
are connected to both the 8259A IRQ inputs and the inputs of the
scheme for a system with two I/O APICs.