Assignment Of I/O Interrupts To The Apic I/O Unit; Default Configuration Interrupt Assignments - Intel MultiProcessor Specification

MultiProcessor Specification
should be cross-connected between the BSP and AP processors. Although the INIT pin is cross-
connected between BSP and AP, a targeted INIT IPI initializes only the targeted processor, because
the INIT IPI does not cause the INIT pin to change state.
The interconnection of I/O APIC interrupt lines is the same as for the 82489DX APIC
configuration. However, for PCI system implementations based on the Intel PCI chipset, the PCI
PIRQx lines are mapped to the ISA IRQx via a mapping register. This type of implementation
makes PCI interrupt lines appear as ISA interrupt lines, which are transparent to the operating
system. All PCI systems defined in the default configurations are of this type. No I/O interrupt
assignment entries are declared for PCI interrupts, as described in Section 4.3.4.

5.3 Assignment of I/O Interrupts to the APIC I/O Unit

The typical APIC I/O unit has 16 general-purpose interrupt inputs. Table 5-2 shows how the
interrupt request line (IRQ) assignments are connected to the I/O APIC in each of the default
configurations.
Table 5-2. Default Configuration Interrupt Assignments
First I/O
APIC Config
INTINx 1
INTIN0 8259A
INTR
INTIN1 IRQ1
INTIN2 IRQ0
INTIN3 IRQ3
INTIN4 IRQ4
INTIN5 IRQ5
INTIN6 IRQ6
INTIN7 IRQ7
INTIN8 IRQ8
INTIN9 IRQ9
INTIN10 IRQ10
INTIN11 IRQ11
INTIN12 IRQ12
INTIN13 IRQ13
INTIN14 IRQ14
INTIN15 IRQ15
NOTE:
N/C designates not connected.
5-6
Config Config Config
2 3 4
8259A 8259A 8259A
INTR INTR INTR
IRQ1 IRQ1 IRQ1
N/C IRQ0 IRQ0
IRQ3 IRQ3 IRQ3
IRQ4 IRQ4 IRQ4
IRQ5 IRQ5 IRQ5
IRQ6 IRQ6 IRQ6
IRQ7 IRQ7 IRQ7
IRQ8 IRQ8 IRQ8
IRQ9 IRQ9 IRQ9
IRQ10 IRQ10 IRQ10
IRQ11 IRQ11 IRQ11
IRQ12 IRQ12 IRQ12
N/C IRQ13 IRQ13
IRQ14 IRQ14 IRQ14
IRQ15 IRQ15 IRQ15
Config Config Config
5 6 7
8259A 8259A N/C
INTR INTR
IRQ1 IRQ1 IRQ1
IRQ0 IRQ0 IRQ0
IRQ3 IRQ3 IRQ3
IRQ4 IRQ4 IRQ4
IRQ5 IRQ5 IRQ5
IRQ6 IRQ6 IRQ6
IRQ7 IRQ7 IRQ7
IRQ8 IRQ8 IRQ8
IRQ9 IRQ9 IRQ9
IRQ10 IRQ10 IRQ10
IRQ11 IRQ11 IRQ11
IRQ12 IRQ12 IRQ12
IRQ13 IRQ13 IRQ13
IRQ14 IRQ14 IRQ14
IRQ15 IRQ15 IRQ15
Comments
INTR output from
master 8259A or
equivalent
Keyboard controller
buffer full
8254 Timer
Real time clock
Floating point
exception and
DMA chaining
Version 1.4