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Virtual Wire Mode Via I/O Apic - Intel MultiProcessor Specification

Intel multiprocessor specification
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MultiProcessor Specification
Figure 3-3 shows how Virtual Wire Mode can be implemented through the BSP's local APIC. It is
also permissible to program the I/O APIC for Virtual Wire Mode, as shown in Figure 3-4. In this
case the interrupt signal passes through both the I/O APIC and the BSP's local APIC.
REG.
MARK
LINTIN1
LINTIN0
RESET
ICC BUS
NMI
INTERRUPT INPUTS
SHADED AREAS INDICATE UNUSED CIRCUITS. DOTTED LINE SHOWS INTERRUPT PATH.
3-10
BSP
CPU 1
NMI
INTR
NMI INTR
LOCAL
APIC
1
LINTIN0
LINTIN1
LINTIN0
EQUIVALENT
Figure 3-4. Virtual Wire Mode via I/O APIC
AP1
CPU 2
CPU 3
NMI INTR
LOCAL
LOCAL
APIC
APIC
2
LINTIN1
LINTIN0
8259A-
INTR
PICS
AP2
3
LINTIN1
I/O
APIC
Version 1.4

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