Interrupt Type Values; I/O Interrupt Entry Fields - Intel MultiProcessor Specification

MultiProcessor Specification
Table 4-10. I/O Interrupt Entry Fields
Field
ENTRY TYPE
INTERRUPT TYPE
PO
EL
SOURCE BUS ID
SOURCE BUS IRQ
DESTINATION I/O APIC ID
DESTINATION I/O APIC INTIN#
4-14
Offset Length
(in bytes:bits) (in bits)
0 8
1 8
2:0 2
2:2 2
4 8
5 8
6 8
7 8
Description
Entry type 3 identifies an I/O interrupt
entry.
See Table 4-11 for values.
Polarity of APIC I/O input signals:
00 = Conforms to
specifications of bus (for
example, EISA is active-
low for level-triggered
interrupts)
01 = Active high
10 = Reserved
11 = Active low
Must be 00 if the 82489DX is used.
Trigger mode of APIC I/O input signals:
00 = Conforms to
specifications of bus (for
example, ISA is edge-
triggered)
01 = Edge-triggered
10 = Reserved
11 = Level-triggered
Identifies the bus from which the interrupt
signal comes.
Identifies the interrupt signal from the
source bus. Values are mapped onto
source bus signals, starting from zero. A
value of 0, for example, would indicate
IRQ0 of an ISA bus. See Section D.3 for
PCI bus semantics.
Identifies the I/O APIC to which the signal
is connected. If the ID is 0FFh, the signal
is connected to all I/O APICs.
Identifies the INTIN n pin to which the
signal is connected.
Version 1.4