Default Configuration For Integrated Apic - Intel MultiProcessor Specification

PENTIIUM (735\90, 815\100)
APICEN
REG.
MARK
NMI
INIT
SMI#
IRQ1
A
8254 TIMER
IRQ8#
IRQ13
B
EISA DMA CHAINING
FROM BSP
FERR#
FERR
IGNNE#
SAMPLING
ABFULL
ABFULL
(PS/2 MOUSE) SAMPLING
PIRQ0-3
C
EDGE/LEVEL TRIGGER
POLARITY CONTROL
IRQ3-7,
IRQx
9-12,14,15
LITMx
LITM3-7,
9-12,14,15
SHADED AREAS:
A,B: MAY NOT BE EXTERNALIZED WITH SOME EISA CHIPSETS
B,C: EISA BUS SPECIFIC
D: PCI BUS SPECIFIC
Figure 5-2. Default Configuration for Integrated APIC
Two local interrupt input pins, LINT0 and LINT1, are shared with the INTR and NMI pins,
respectively. The LINT0, LINT1, SMI# and INIT signals are switched by APICEN, and they
Version 1.4
BSP
CPU1
APICEN
LOCAL
APIC
INTR/LINT0
NMI/LINT1
INIT
SMI#
ICC BUS
3
4
5
6
7
INT8
9
10
11
13
14
15
3
4
5
6
7
12
9
10
11
D
12
PIRQ
14
MAPPING 15
3-7,9-11,14,15
Default Configurations
AP
PENTIUM (735\90, 815\100)
CPU2
LOCAL
APIC
0
1
2
3
4
5
6
I/O
7
APIC
8
9
10
11
12
13
14
15
0
1
2
MASTER
INTR
3
8259A PIC
4
5
6
7
0
1
2
SLAVE
3
8259A PIC
4
5
6 IMCR
7
E0
5-5