I/O Interrupt Entry - Intel MultiProcessor Specification

2. No Interrupt Assignment Entries are declared for any of the bus source interrupts, and the
operating system uses some other bus-specific knowledge of bus interrupt schemes in order to
support the bus. This operating system bus-specific knowledge is beyond the scope of this
specification.
31
DESTINATION
I/O APIC INTIN#
31
Version 1.4
24 23 16 15
DESTINATION SOURCE BUS
I/O APIC ID
I/O INTERRUPT FLAG
INTERRUPT
E P
RESERVED
L O
24 23 16 15
Figure 4-7. I/O Interrupt Entry
MP Configuration Table
8 7 0
SOURCE
04H
IRQ BUS ID
ENTRY TYPE
00H
TYPE 3
8 7 0
4-13