82489DX: The 82489DX Advanced Programmable Interrupt Controller (APIC).
8259A: The 8259A Programmable Interrupt Controller (PIC) or its equivalent.
AP: Application processor, one of the processors not responsible for system initialization.
APIC: Advanced Programmable Interrupt Controller, either the 82489DX APIC or the integrated
APIC on Pentium processors.
BIOS: Basic Input/Output Subsystem.
BSP: Bootstrap processor, the processor responsible for system initialization.
Cache coherency: A property of a cache/memory system that guarantees that a request for an item
from memory will retrieve the most up-to-date value of that item, regardless of what cache or
memory location currently holds that value.
CMOS RAM: The battery backed-up configuration memory of the PC/AT motherboard.
DP: A dual processor system is one with two processors.
ExtINT: A delivery mode of the Local Vector Table of a local APIC that causes delivery of a
signal to the INT pin of the processor as an interrupt that originated in an externally connected
8259A-equivalent PIC. The ExtINTA output signal is also asserted. The INTA cycle that
corresponds to the ExtINT delivery should be routed to the external PIC that is expected to supply
Flush: Write back all modified lines of a cache.
INIT: Unless otherwise specified, the processor-specific reset or system-wide soft reset functions.
This definition is functional and sometimes bears no relationship to the actual signal name. For
example, the term "INIT" may refer to the INIT signal on the Pentium processor or to the RESET
signal on the Intel486 processor.
INIT IPI: A type of APIC interprocessor interrupt whose delivery mode is set to RESET. Upon
delivery to the specified destinations, the destination APICs assert their PRST output signals.
When the PRST lines are connected to the INIT or RESET inputs of their respective processors, an
INIT IPI causes reinitialization of the destination processors.
Invalidate: Change the state of a cache line to the Invalid state.
IPI: Interprocessor interrupt.
MESI: A cache coherency protocol named after the states that cache lines may have: Modified,
Exclusive, Shared, Invalid.
MP: A multiprocessor system is one with two or more processors.
PIC: Programmable Interrupt Controller.