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Constructing The Mp Configuration Table - Intel MultiProcessor Specification

Intel multiprocessor specification
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MultiProcessor Specification
mov
mov
and
or
mov
;
; Program LVT2 as NMI, which delivers the signal on the NMI signal of all
; processors' cores listed in the destination.
;
mov
mov
and
or
mov
extrn
call
pop
out
pop
out
pop
pop
pop
ret
InitLocalAPIC
Example A-1. Programming Local APIC for Virtual Wire Mode (continued)
A.4 Constructing the MP Configuration Table
For a compliant system, one of the main functions of the system BIOS is to construct the MP
floating pointer structure and the MP configuration table. Because the MP configuration table is
optional, the BIOS must set the MP feature information bytes in the MP floating pointer structure
to indicate whether an MP configuration table is present.
If the MP configuration table is required, the BIOS constructs it in conjunction with the BSP and
APs. The BIOS is responsible for synchronizing the activities of the APs during the construction
of the table. The BIOS may need some synchronization during processor initialization so that each
processor may be brought up in the proper order. The mechanism for synchronization is not
specified; however, the procedure described in the following paragraphs of this section uses AP
status flags as an example of a synchronization mechanism. This procedure also initializes the APs
serially. System developers may employ other mechanisms and may initialize all processors in
parallel to minimize the system start-up time.
The BIOS maintains an initialized AP status flag for each AP. Each AP will begin executing the
same BIOS code as the BSP, but will eventually be put in a HALT state or held in a loop until the
BSP enables its AP status flag.
A-4
esi,LVT1
eax,[esi]
eax,0FFFE00FFH
eax,000005700H
[esi],eax
esi,LVT2
eax,[esi]
eax,0FFFE00FFH
eax,000005400H
[esi],eax
pmode_off : near
pmode_off
ax
0a1h,al
ax
021h,al
esi
es
ds
endp
; read LVT1
; not masked, edge, active high
; ExtInt
; write LVT1
; read LVT2
; not masked, edge, active high
; NMI
; write LVT2
; switch back to real mode
; restore imr settings
; restore secondary imr
; restore primary imr
; this routine leaves NMI disabled
; restore regs used in APIC init
; (unless also saved for CPUID)
Version 1.4

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