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Intel MultiProcessor Specification page 92

Intel multiprocessor specification
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MultiProcessor Specification
Table 4-14. System Address Space Mapping Entry Fields
Field
ENTRY TYPE
ENTRY LENGTH
BUS ID
ADDRESS TYPE
ADDRESS BASE
LENGTH
If any main memory address is mapped to a software visible bus, such as PCI, it must be explicitly
declared using a System Address Space Mapping entry.
In the case of a bus that is directly connected to the main system bus, system address space records
and compatibility base address modifiers must be provided as needed to fully describe the complete
set of addresses that are mapped to that bus. For example, in Figure 4-10, complete explicit
descriptions must be provided for PCI BUS 0 and PCI BUS 1 even if one of the buses is
programmed for subtractive decode.
Figure 4-10. Example System with Multiple Bus Types and Bridge Types
E-4
Offset
Length
(in bytes:bits)
(in bits)
0
8
1
8
2
8
3
8
4
64
12
64
Processor 0
System Bus
PCI
Host Bridge
PCI Bus 0
EISA Bridge
EISA Bus
Description
Entry type 128 identifies a System Address Space
Mapping Entry.
A value of 20 indicates that an entry of this type is
twenty bytes long.
The BUS ID for the bus where the system address
space is mapped. This number corresponds to the
BUS ID as defined in the base table bus entry for
this bus.
System address type used to access bus
addresses must be:
0 = I/O address
1 = Memory address
2 = Prefetch address
All other numbers are reserved.
Starting address
Number of addresses which are visible to the bus
Processor 1
Memory
Controller
PCI
Host Bridge
PCI Bus 1
PCI-to-PCI
Bridge
PCI Bus 2
Version 1.4

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