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Intel MultiProcessor Specification page 96

Intel multiprocessor specification
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MultiProcessor Specification
PIC Mode: One of three interrupt modes defined by the MP specification. In this mode the APICs
are effectively disabled, while interrupts are generated by 8259A-equivalent PICs and delivered
directly to the BSP. This is a uniprocessor compatibility mode.
POST: Power-On Self Test, the first BIOS procedure executed after a RESET or INIT.
RESET: The system-wide hard reset. This definition is functional. It may refer to the RESET
signal on both Pentium and Intel486 processors or the RESET signal of the 82489DX APIC.
Shutdown code: The value of CMOS RAM location 0Fh, which indicates that reason that a
RESET was performed.
STARTUP IPI: A type of APIC interprocessor interrupt that is similar to an NMI with an
embedded vector. It does not cause any change of state, but merely causes the targeted processor
to start executing in Real Mode from address 000VV000h, VV being an 8-bit vector which is part
of the IPI message. Startup vectors are limited to a 4K page boundary in the first 1 MB of the
address space. STARTUP IPIs are not maskable, and can be issued at any time. The benefit of
STARTUP-IPI compared to NMI is that it does not require the targeted APIC to be enabled, and it
does not require the interrupt table to be programmed. Thus, the operating system's initialization
procedure can use it to wake up an AP that has been sleeping since RESET or INIT. The
STARTUP IPI is not supported by the 82489DX APIC.
Symmetric I/O Mode: One of three interrupt modes defined by the MP specification. In this
mode, the APICs are fully functional, and interrupts are generated and delivered to the processors
by the APICs. Any interrupt can be delivered to any processor. This is the only multiprocessor
interrupt mode.
Symmetry: The relationship of equality among components of a multiprocessor system in which
no processor is special with respect to its access to memory, interrupts, or I/O. For interrupts,
symmetry means that any interrupt from any source can be routed to any processor and handled
there. For I/O, it means that all I/O control registers, be they in memory space, I/O space, or some
other special address space, are accessible to all processors. Per-processor control hardware, such
as interrupt controllers or processor identification registers, must be at the same physical address
for all processors.
Virtual Wire Mode: One of three interrupt modes defined by the MP specification. In this mode
interrupts are generated by the 8259A-equivalent PICs, but delivered to the BSP by an APIC that is
programmed to act as a "virtual wire"; that is, the APIC is logically indistinguishable from a
hardwired connection. This is a uniprocessor compatibility mode.
Warm reset: A technique that allows the RESET or INIT signal to be asserted without actually
causing the BIOS to run through its entire initialization procedure. If a value of 0Ah is placed in
the shutdown code, the first instructions of the BIOS POST procedure read the warm-reset vector
from system RAM location 40:67h, and jump to that address.
Write-back: A cache update policy wherein a modified cache line is not written back to main
memory until the last possible instant—when another processor needs to access the data or when
its location in the cache is needed for other data.
Version 1.4



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