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Bus Hierarchy Descriptor Entries - Intel MultiProcessor Specification

Intel multiprocessor specification
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4.4.2
Bus Hierarchy Descriptor Entry
If present, Bus Hierarchy Descriptor entries define how I/O buses are connected relative to each
other in a system with more than one I/O bus. Bus Hierarchy Descriptors are used to supplement
System Address Mapping entries to describe how addresses propagate to particular buses in
systems where address decoding cannot be completely described by System Address Space
Mapping entries alone. Entries of this type are required for each bus that is connected to the
system hierarchically below another I/O bus. For example, given the system described in
Figure 4-10, bus hierarchy entries are required for the EISA bus and the PCI BUS 2 since both
have parent buses that are themselves I/O buses.
The Bus Hierarchy entry provides information about where in a hierarchical connection scheme a
given bus is connected and the type of address decoding performed for that bus. Figure 4-11 shows
the format of each entry, and Table 4-15 explains each field. See also Appendix E, for more
information.
31
31
Version 1.4
28
27
24
23
20
19
16
RESERVED
B U S IN FO
B U S ID
S
R ESER VED
D
28
27
24
23
20
19
16
Figure 4-11. Bus Hierarchy Descriptor Entry
15
12
11
8
7
4
3
PA R EN T B U S
EN TR Y TYPE
EN TR Y LEN G TH
129
15
12
11
8
7
4
3
MP Configuration Table
0
04H
00H
0
4-21

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