Intel MultiProcessor Specification page 23

Table 3-1. Memory Cacheability Map
Addresses
(in hex) Size Description
0000_0000h – 640KB Main memory
0009_FFFFh
000A_0000h – 128KB Display buffer for
000B_FFFFh video adapters
000C_0000h – 128KB ROM BIOS for add-on
000D_FFFFh cards
000E_0000h – 128KB System ROM BIOS
000F_FFFFh
0010_0000h – Main memory
0FEBF_FFFFh
Not specified.
devices
0FEC0_0000h – APIC I/O unit
1
0FECF_FFFFh
0FED0_0000h – Reserved for
0FEDF_FFFFh memory-mapped I/O
devices
0FEE0_0000h- APIC Local Unit
1
0FEEF_FFFFh
0FEF0_0000h – Reserved for
0FFFD_FFFFh memory-mapped I/O
devices
0FFFE_0000h – 128KB Initialization ROM
0FFFF_FFFFh
NOTES:
1. These addresses are part of this specification. The other address regions in this table are shown for reference only, and
should not be construed as the sole definition of a PC/AT-compatible address space format or cache.
2. Any memory-mapped device should be shareable unless the nature of the device is that there is one device per
processor.
Version 1.4
Shared by All
Processors?
Yes
Yes
Yes
Yes
Yes
2
Memory-mapped I/O Yes
Yes
2
Yes
No
2
Yes
Yes
Hardware Specification
Cacheable? Comment
Yes
No
Yes
Yes
Yes Maximum address
depends on total memory
installed in the system.
Not Top unused memory
specified
No Refer to the register
description in the APIC
data book.
Not
specified
No Refer to the register
description in the APIC
data book.
Not
specified
Not
specified
3-3