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Fixed Interrupt Routing - Intel MultiProcessor Specification

Intel multiprocessor specification
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MultiProcessor Specification
If IMCR is implemented but the system includes one or more I/O APICs that are not controlled
through IMCR, the hardware must accomplish routing changes for such I/O APICs by some other
means when the system switches into symmetric I/O mode. These routing changes must be done
without requiring any additional intervention from software.
For systems without the IMCR register, the routing of the PCI interrupts to the EISA/ISA IRQ
must be automatically disabled as the I/O APICs are programmed. Therefore, when the operating
system programs the I/O APICs in accordance with the MP configuration table, the hardware must
detect this operation and disable the routing mechanism without additional intervention by the
operating system. This operation can be done globally for an entire system as soon as any APIC
interrupts are enabled or it can be done on an interrupt-by-interrupt basis.
D.1.2

Fixed Interrupt Routing

Several implementations of fixed interrupt routing are possible, depending on hard wiring, via
jumpers for example, or software means, such as chipset-specific registers. Since these
implementations have no mechanism to disable the PCI interrupt to EISA/ISA IRQ routing, the
MP configuration table must be set up carefully to avoid problems with duplicate interrupt
mappings in symmetric I/O mode.
To avoid such problems on systems with fixed routing, PIC or Virtual Wire Mode interrupt
routings must not be used by software when the system is in symmetric mode, since these routings
cannot be disabled or altered. This situation implies two restrictions that must be placed on the
way PCI interrupts are routed to EISA/ISA IRQs and on that way the MP configuration table is
built:
If a PCI interrupt is routed to an EISA/ISA IRQ that is used by an EISA/ISA device, that PCI
interrupt must be delivered through the same I/O APIC input as that EISA/ISA IRQ. The
connection from the PCI interrupt to the additional I/O APIC input must not be entered in the
MP configuration table.
If a PCI interrupt is routed to an EISA/ISA IRQ which is NOT used by an EISA/ISA device,
that PCI interrupt must be delivered through its individual I/O APIC connection, and the
connection of that EISA/ISA IRQ to its I/O APIC input should not be entered in the MP
configuration table.
As an example, take a system with two I/O APICs, a PCI bus, and an EISA bus. Each EISA IRQ
is connected to an input of one I/O APIC and each PCI interrupt is connected to the other I/O
APIC. A fixed interrupt routing design could connect all PCI interrupts to a single EISA interrupt.
This design does not give optimum performance, because PCI interrupts must be shareable, but it
does allow all interrupts to be properly handled.
If an EISA device is connected to the same interrupt, the MP configuration table would not contain
any entries for the second I/O APIC. The second I/O APIC is not used.
If no EISA device uses that interrupt, however, the MP configuration table could contain an entry
for each PCI interrupt, describing its connection to the second I/O APIC. The EISA IRQ used by
the PCI interrupts in PIC mode would not have an entry in the table. All other EISA IRQs would
have an entry in the table describing connections to the first I/O APIC.
D-2
Version 1.4

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