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Bus Hierarchy Descriptor Entry - Intel MultiProcessor Specification

Intel multiprocessor specification
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MultiProcessor Specification
Table 4-15 Bus Hierarchy Descriptor Entry Fields
Field
ENTRY TYPE
ENTRY LENGTH
BUS ID
BUS INFORMATION:SD
PARENT BUS
For buses where the BUS INFORMATION:SD bit is set, System Address Mappings may not be
needed. Since the bus is defined as being subtractive decode, the range of addresses that appear on
the bus can be derived from address decoding information for parent and peer buses.
E-6
31
28
27
24
23
20
19
RESERVED
BUS INFO
BUS ID
S
RESERVED
D
31
28
27
24
23
20
19
Figure 4-11. Bus Hierarchy Descriptor Entry
Offset
Length
(in bytes:bits)
(in bits)
0
8
1
8
2
8
3:0
1
4
8
16
15
12
11
8
7
4
3
PARENT BUS
ENTRY TYPE
ENTRY LENGTH
129
16
15
12
11
8
7
4
3
Description
Entry type 129 identifies a Bus Hierarchy Descriptor
Entry.
A value of 8 indicates that this entry type is eight
bytes long.
The BUS ID identity of this bus. This number
corresponds to the BUS ID as defined in the base
table bus entry for this bus.
Subtractive Decode Bus. If set, all addresses visible
on the parent bus but not claimed by another device
on the parent bus (including bridges to other
buses) are useable on this bus.
Parent Bus. This number corresponds to the BUS
ID as defined in the base table bus entry for the
parent bus of this bus
0
04H
00H
0
Version 1.4

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