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Local Interrupt Entry Fields - Intel MultiProcessor Specification

Intel multiprocessor specification
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MultiProcessor Specification
Table 4-12. Local Interrupt Entry Fields
Field
ENTRY TYPE
INTERRUPT TYPE
PO
EL
SOURCE BUS ID
SOURCE BUS IRQ
DESTINATION LOCAL APIC ID
DESTINATION LOCAL APIC
LINTIN#
4-16
Offset (in
Length
bytes:bits)
(in bits) Description
0
8
Entry type 4 identifies a local interrupt
entry.
1
8
See Table 4-11 for values
2:0
2
Polarity of APIC local input signals:
Must be 00 if the 82489DX is used.
2:2
2
Trigger mode of APIC local input signals:
4
8
Identifies the bus from which the interrupt
signal came.
5
8
Identifies the interrupt signal from the
source bus. Values are mapped onto
source bus signals, starting from zero. A
value of 0, for example, would indicate
IRQ0 of an ISA bus.
PCI bus semantics.
6
8
Identifies the local APIC to which the
signal is connected. If the ID is 0FFh, the
signal is connected to all local APICs.
Identifies the LINTIN n pin to which the
7
8
signal is connected, where n = 0 or 1.
00 =
Conforms to
specifications of bus
(for example, EISA is
active-low for level
triggered interrupts)
01 =
Active high
10 =
Reserved
11 =
Active low
00 =
Conforms to
specifications of bus
(for example, ISA is
edge triggered)
01 =
Edge-triggered
10 =
Reserved
11 =
Level-triggered
See Section D.3 for
Version 1.4

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