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System-Wide Init; Processor-Specific Init - Intel MultiProcessor Specification

Intel multiprocessor specification
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or by the front panel reset button (if the system is so equipped). This type of reset operates without
regard to cycle boundaries, and, for example, is connected to the RESET pin of Pentium

System-wide INIT

The system-wide INIT, as defined by this specification, refers to a soft or warm reset that
initializes only portions of the processor. This type of reset initializes the microprocessor in such a
way that the reset does not corrupt any pending cycles, but waits instead for a cycle boundary, and
does not invalidate the contents of caches and floating point registers. This type of reset request is
connected to the INIT signal of newer processors, such as the Pentium processors. On Intel486
processors, the RESET pin is used for this function, as well as for hard resets, but the RESET pin
does not provide the advantages of the INIT pin. There are
reset, including:
A write either to a port of the 8042 Keyboard Controller or to some other port provided for the
same purpose by a chipset.
A shutdown special bus cycle. Usually a chipset senses a shutdown cycle and asserts a soft
reset to the processor.
In a compliant system, the standard PC/AT-platform resets mentioned above, both hard and soft,
must be directed to all processors in the system, except in the case of fault-tolerant MP systems, in
which a soft reset may be handled on a per-processor basis.

Processor-specific INIT

A processor-specific INIT is one of the basic multiprocessor support functions of a compliant
multiprocessor system, along with processor startup and shutdown. With it, the BSP can
selectively initialize an AP for subsequent startup or recover an AP from a fatal system error. This
type of INIT function is exclusively used by the MP operating system or BIOS self-test routine.
The system must be designed so that the processor-specific INIT can be initiated by software
programming; it is not necessary that it be initiated by hardware.
A compliant system supports the processor-specific INIT via a special interprocessor interrupt (IPI)
mechanism called INIT IPI. For the 82489DX APIC, INIT IPI is an IPI that has the delivery mode
RESET, which delivers the signal to all processors listed in the destination by asserting/deasserting
the addressed APIC local unit's PRST output pin. When the PRST signal is connected to the INIT
pin of the Pentium processor or to the RESET pin of the Intel486 processor, the INIT IPI forces the
processor to begin executing at the reset vector.
For systems based on the Intel486 processor, the 82489DX APIC's PRST line must be the only
line connected to the processor's RESET input, so that the INIT IPI resets the targeted processor
only. The system reset signal is connected to the local 82489DX APIC's RESET input. Assertion
of the system reset signal then causes all of the local 82489DX APICs to assert their PRST outputs,
thereby resetting all the processors.
For integrated APIC versions of the Pentium processor, INIT IPI asserts and deasserts the internal
INIT signal of the Pentium processor.
Version 1.4
Hardware Specification
many possible
ways to assert



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