Default Configuration For Discrete Apic - Intel MultiProcessor Specification

A
IMCR
E0
REG.
MARK
NMI
INTR
RESET
ICC BUS
I/O BUS
NMI
IRQ1
B
8254 TIMER
IRQ8#
IRQ13
C
EISA DMA CHAINING
FROM BSP
FERR#
FERR
IGNNE#
SAMPLING
ABFULL ABFULL
(PS/2 MOUSE) SAMPLING
D
EDGE/LEVEL TRIGGER
POLARITY CONTROL
IRQ3-7,
9-12,14,15
IRQx
LITMx
LITM3-7,
9-12,14,15
SHADED AREAS:
A: OPTIONAL IF VIRTUAL WIRE MODE IS IMPLEMENTED
B,C: MAY NOT BE EXTERNALIZED WITH SOME EISA CHIPSETS
C,D: EISA BUS SPECIFIC
Figure 5-1. Default Configuration for Discrete APIC
Version 1.4
BSP
INTEL486
CPU 1
NMI INTR RESET
ExtINTA
PNMI PINT PRST
LOCAL
82489DX APIC
INTA
TRAP
LINTIN0 LINTIN1
3
4
5
6
7
8
9
10
11
13
14
15
3
4
5
6
7
12
9
10
11
14
15
12
Default Configurations
AP2
INTEL486
CPU 3
NMI INTR RESET
ExtINTA
PNMI PINT PRST
LOCAL
82489DX APIC
INTA
TRAP
LINTIN0 LINTIN1
0
1
2
3
4
5
I/O
6
7
82489DX
8
APIC
9
10
11
12
13
14
15
GLUE
0
1
2
MASTER INTR
3
8259A PIC
4
5
6
7
INTA
0
1
2
SLAVE
3
8259A PIC
4
5
6
7
5-3