Processor Entries; Processor Entry - Intel MultiProcessor Specification

Table 4-3. Base MP Configuration
Entry Description
Processor
Bus
I/O APIC
I/O Interrupt Assignment
Local Interrupt Assignment
* All other type codes are reserved.

4.3.1 Processor Entries

Figure 4-4 shows the format of each processor entry, and Table 4-4 defines the fields.
In systems that use the MP configuration table, the only restriction placed on the assignment of
APIC IDs is that they
for only APIC IDs 0, 2, and 4 to be present.
Version 1.4
Table Entry Types
Entry Type Code*
0
1
2
3
4
31 28 27 24 23 20 19
RESERVED
RESERVED
FEATURE FLAGS
CPU SIGNATURE
CPU FLAGS
LOCAL APIC
B E
VERSION #
RESERVED P N
31 28 27 24 23 20 19
Figure 4-4. Processor Entry
be unique. They do not need to be consecutive. For example, it is possible
Length
(in bytes) Comments
20 One entry per processor.
8 One entry per bus.
8 One entry per I/O APIC.
8 One entry per bus interrupt source.
8 One entry per system interrupt
source.
16 15 12 11 8 7 4 3
ENTRY TYPE
LOCAL APIC ID
0
16 15 12 11 8 7 4 3
MP Configuration Table
0
10H
0CH
08H
04H
00H
0
4-7