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Intel MultiProcessor Specification page 7

Intel multiprocessor specification
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A.1
BIOS Post Initialization ............................................................................A-1
A.2
Controlling the Application Processors ....................................................A-2
A.3
Programming the APIC for Virtual Wire Mode .........................................A-2
A.4
Constructing the MP Configuration Table................................................A-4
B.1
Operating System Boot-up .......................................................................B-1
B.2
Operating System Booting and Self-configuration ....................................B-2
B.3
Interrupt Mode Initialization and Handling ................................................B-2
B.4
Application Processor Startup ..................................................................B-3
B.4.1
USING INIT IPI ............................................................................B-4
B.4.2
USING STARTUP IPI...................................................................B-5
B.5
AP Shutdown Handling.............................................................................B-5
B.6
Other IPI Applications ...............................................................................B-6
B.6.1
Handling Cache Flush..................................................................B-6
B.6.2
Handling TLB Invalidation ............................................................B-6
B.6.3
Handling PTE Invalidation............................................................B-6
B.7
Spurious APIC Interrupts ..........................................................................B-6
B.8
Supporting Unequal Processors ...............................................................B-7
D.1
Interrupt Routing with Multiple APICs .......................................................D-1
D.1.1
Variable Interrupt Routing ............................................................D-1
D.1.2
Fixed Interrupt Routing ................................................................D-2
D.2
Bus Entries in Systems with More Than One PCI Bus .............................D-3
D.3
I/O Interrupt Assignment Entries for PCI Devices.....................................D-3
Contents
vii

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