Design Example Detailed Description; Features - Intel F-Tile SDI II Agilex User Manual

710496 | 2022.01.28
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2. Design Example Detailed Description

The SDI II Intel FPGA IP core includes the following design examples for Intel Agilex
F-tile devices.
• Parallel loopback with external VCXO
• Serial loopback
Note: Only Single-Rate design examples are available in the Intel Quartus Prime 21.4
software. Multi-rate design will be available in a future Intel Quartus Prime release.

2.1. Features

1. LED status for early debugging stage with RX or TX only options.
2. To use RX or TX only components, remove the irrelevant blocks from the simplex
version serial loopback design as described in the following table.
Table 5. Features
User Require
RX only
TX only
(2)
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Preserve
• RX top
• Reference and System PLL Clocks
IP
• DR IP & DR arbiter (if present)
• Device Init
• TX top
• Reference and System PLL Clocks
IP
• DR IP & DR arbiter (if present)
• Device Init
Remove
TX Top
RX Top
ISO
9001:2015
Registered
(2)