Processor Configuration Registers
Table 77.
VC0RCAP - VC0 Resource Capability (Sheet 2 of 2)
Bit
Access
22:16
RO
15
RO
14:8
RO
7:0
RO
6.3.6
VC0RCTL - VC0 Resource Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Controls the resources associated with PCI Express Virtual Channel 0.
®
TM
Intel
Core
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
August 2010
Document Number: 323178-003
Default
RST/PWR
Value
00h
Core
0b
Core
00h
Core
01h
Core
Description
Reserved for Maximum Time Slots
Reject Snoop Transactions (RSNPT):
Reject Snoop Transactions (RSNPT):
0: Transactions with or without the No Snoop bit set within
the TLP header are allowed on this VC.
1: When Set, any transaction for which the No Snoop
attribute is applicable but is not Set within the TLP Header
is rejected as an Unsupported Request
Reserved
Port Arbitration Capability (PAC)
Port Arbitration Capability – Indicates types of Port
Arbitration supported by the VC resource. This field is valid
for all Switch Ports, Root Ports that support peer-to to-
peer traffic, and RCRBs, but not for PCI Express Endpoint
devices or Root Ports that do not support peer to peer
traffic. Each bit location within this field corresponds to a
Port Arbitration Capability defined below. When more than
one bit in this field is Set, it indicates that the VC resource
can be configured to provide different arbitration services.
Software selects among these capabilities by writing to the
Port Arbitration Select field (see below). Defined bit
positions are:
Bit 0 Non-configurable hardware-fixed arbitration scheme,
e.g., Round Robin (RR)
Bit 1 Weighted Round Robin (WRR) arbitration with 32
phases
Bit 2 WRR arbitration with 64 phases
Bit 3 WRR arbitration with 128 phases
Bit 4 Time-based WRR with 128 phases
Bit 5 WRR arbitration with 256 phases
Bits 6-7 Reserved MCH default indicates "Non-configurable
hardware-fixed arbitration scheme".
0/6/0/MMR
114-117h
800000FFh
RO; RW;
32 bits
®
®
Celeron
Processor P4505, U3405 Series
Datasheet Addendum
137
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