AMD Geode SC1200 Data Book page 88

32579B
Bit Description
Offset 1Eh-1Fh
This register controls the configuration of the core clock multiplier and the reference clocks.
15:14 Reserved.
13 Reserved. Must be set to 0.
12 Reserved. Must be set to 0.
11:10 Reserved.
9:8 FPCICK (Internal Fast-PCI Clock). (Read Only) Reflects the internal Fast-PCI clock and is the input to the GX1 module
that is used to generate the core clock. These bits reflect the value of strap pins CLKSEL[1:0].
00: 33.3 MHz
01: 48 MHz
10: 66.7 MHz
11: 33.3 MHz
7:4 Reserved.
3:0 MVAL (Multiplier Value). This 4-bit value controls the multiplier in ADL. The value is set according to the Maximum Clock
Multiplier bits of the MCCM register (Offset 10h). The multiplier value should never be written with a multiplier which is differ-
ent from the multiplier indicated in the MCCM register.
0100: Multiply by 4
0101: Multiply by 5
0110: Multiply by 6
0111: Multiply by 7
1000: Multiply by 8
1001: Multiply by 9
1010: Multiply by 10
Other: Reserved
88
Table 4-8. Clock Generator Configuration (Continued)
Core Clock Frequency Control Register - CCFC (R/W)
General Configuration Block
Reset Value: Strapped Value
AMD Geode™ SC1200/SC1201 Processor Data Book