Strap Options; Table 3-4. Strap Options - AMD Geode SC1200 Data Book

32579B
3.2

Strap Options

Several balls are read at power-up that set up the state of
the SC1200/SC1201 processor. These balls are typically
multiplexed with other functions that are outputs after the
power-up sequence is complete. The SC1200/SC1201 pro-
cessor must read the state of the balls at power-up and the
internal PU or PD resistors do not guarantee the correct
state will be read. Therefore, it is required that an external
Strap Option Muxed With
CLKSEL0 RD#
CLKSEL1 SOUT1
CLKSEL2 SOUT2
CLKSEL3 SYNC
BOOT16 ROMCS#
TFT_PRSNT SDATA_OUT
LPC_ROM PCICLK1
FPCI_MON PCICLK0
DID0 GNT0#
DID1 GNT1#
Note: Accuracy of internal PU/PD resistors: 80K to 250K.
Location of the GCB (General Configuration Block) cannot be determined by software. See the AMD Geode™ SC1200/SC1201
Processor Specification Update document.
44

Table 3-4. Strap Options

Nominal External PU/PD Strap Settings
Internal
Ball No. PU or PD Strap = 0 (PD)
B8 PD See Table 4-7 on page 85 for
100
CLKSEL strap options.
AF3 PD
100
D29 PD
100
P30 PD
100
C8 PD Enable boot
100
from 8-bit ROM
P29 PD TFT not muxed
100
onto Parallel
Port
D6 PD Disable boot
100
from ROM on
LPC bus
A4 PD Disable Fast-
100
PCI, INTR_O,
and SMI_O
monitoring sig-
nals.
C5 PD Defines the system-level chip ID.
100
C6 PD
100
PU or PD resistor with a value of 1.5 KΩ be placed on the
balls listed in Table 3-4. The value of the resistor is impor-
tant to ensure that the proper state is read during the
power-up sequence. If the ball is not read correctly at
power-up, the SC1200/SC1201 processor may default to a
state that causes it to function improperly, possibly result-
ing in application failure.
Strap = 1 (PU) Register References
GCB+I/O Offset 1Eh[9:8] (aka CCFC register
bits [9:8]) (RO): Value programmed at reset
by
CLKSEL[1:0].
GCB+I/O Offset 10h[3:0] (aka MCCM regis-
ter bits [3:0]) (RO): Value programmed at
reset by
CLKSEL[3:0].
GCB+I/O Offset 1Eh[3:0] (aka CCFC register
bits [3:0]) (R/W, but write not recommended):
Value programmed at reset by CLKSEL[3:0].
Note: Values for GCB+I/O Offset 10h[3:0]
and 1Eh[3:0] are not the same.
Enable boot GCB+I/O Offset 34h[3] (aka MCR register bit
from 16-bit 3) (RO): Reads back strap setting.
ROM
GCB+I/O Offset 34h[14] (R/W): Used to allow
the ROMCS# width to be changed under pro-
gram control.
TFT muxed GCB+I/O Offset 30h[23] (aka PMR register
onto Parallel bit 23) (R/W): Reads back strap setting.
Port
Enable boot F0BAR1+I/O Offset 10h[15] (R/W): Reads
from ROM on back strap setting and allows LPC ROM to be
LPC bus changed under program control.
Enable Fast- GCB+I/O Offset 34h[30] (aka MCR register
PCI, INTR_O, bit 30) (RO): Reads back strap setting.
and SMI_O
Note: For normal operation, strap this sig-
monitoring sig-
nal low using a 1.5 KΩ resistor.
nals. (Useful
during debug.)
GCB+I/O Offset 34h[31,29] (aka MCR regis-
ter bits 31 and 29) (RO): Reads back strap
setting.
Note: These signals should be connected
to a 1.5 KΩ PD resistor to ensure a
low level at power-up.
AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Definitions