Core Logic Module - Register Summary
F0BAR0+
Width
I/O Offset
(Bits)
Type
00h-03h
32
R/W
04h-07h
32
RO
08h-0Bh
32
R/W
0Ch-0Fh
32
R/W1C
10h-13h
32
R/W
14h-17h
32
RO
18h-1Bh
32
R/W
1Ch-1Fh
32
R/W1C
20h-23h
32
R/W
24h-27h
32
R/W
28h-2Bh
32
R/W
F0BAR1+
Width
I/O Offset
(Bits)
Type
00h-03h
32
R/W
04h-07h
32
R/W
08h-0Bh
32
R/W
0Ch-0Fh
32
R/W
10h-13h
32
R/W
14h-17h
32
R/W
18h-1Bh
32
R/W
1Ch-1Fh
32
R/W
20h-23h
32
RO
AMD Geode™ SC1200/SC1201 Processor Data Book
Table 6-15. F0BAR0: GPIO Support Registers Summary
Name
GPDO0 — GPIO Data Out 0 Register
GPDI0 — GPIO Data In 0 Register
GPIEN0 — GPIO Interrupt Enable 0 Register
GPST0 — GPIO Status 0 Register
GPDO1 — GPIO Data Out 1 Register
GPDI1 — GPIO Data In 1 Register
GPIEN1 — GPIO Interrupt Enable 1 Register
GPST1 — GPIO Status 1 Register
GPIO Signal Configuration Select Register
GPIO Signal Configuration Access Register
GPIO Reset Control Register
Table 6-16. F0BAR1: LPC Support Registers Summary
Name
SERIRQ_SRC — Serial IRQ Source Register
SERIRQ_LVL — Serial IRQ Level Control Register
SERIRQ_CNT — Serial IRQ Control Register
DRQ_SRC — DRQ Source Register
LAD_EN — LPC Address Enable Register
LAD_D0 — LPC Address Decode 0 Register
LAD_D1 — LPC Address Decode 1 Register
LPC_ERR_SMI — LPC Error SMI Register
LPC_ERR_ADD — LPC Error Address Register
32579B
Reset
Reference
Value
(Table 6-30)
FFFFFFFFh
Page 224
FFFFFFFFh
Page 224
00000000h
Page 224
00000000h
Page 224
FFFFFFFFh
Page 225
FFFFFFFFh
Page 225
00000000h
Page 225
00000000h
Page 225
00000000h
Page 225
00000044h
Page 226
00000000h
Page 227
Reset
Reference
Value
(Table 6-31)
00000000h
Page 228
00000000h
Page 229
00000000h
Page 231
00000000h
Page 231
00000000h
Page 232
00080020h
Page 233
00000000h
Page 234
00000080h
Page 234
00000000h
Page 235
179
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