Legacy Functional Blocks; Table 5-33. Parallel Port Register Map For First Level Offset; Table 5-34. Parallel Port Register Map For Second Level Offset - AMD Geode SC1200 Data Book

SuperI/O Module
5.8

Legacy Functional Blocks

This section briefly describes the following blocks that pro-
vide legacy device functions:
• Parallel Port. (Similar to Parallel Port in the National
Semiconductor PC87338.)
• Serial Port 1 and Serial Port 2 (SP1 and SP2), UART
functionality for both SP1 and SP2. (Similar to SCC1 in
the National Semiconductor PC87338.)
• Infrared Communications Port / Serial Port 3 function-
ality. (Similar to SCC2 in the National Semiconductor
PC87338.)
The description of each Legacy block includes a general
description, register maps, and bit maps.

Table 5-33. Parallel Port Register Map for First Level Offset

First Level Offset
000h
000h
001h
002h
003h
004h
005h
006h
007h
400h
400h
400h
400h
401h
402h
403h
404h
405h

Table 5-34. Parallel Port Register Map for Second Level Offset

Second Level Offset
00h
02h
04h
05h
AMD Geode™ SC1200/SC1201 Processor Data Book
Type Name
R/W DATAR. PP Data
W AFIFO. ECP Address FIFO
RO DSR. Status
R/W DCR. Control
R/W ADDR. EPP Address
R/W DATA0. EPP Data Port 0
R/W DATA1. EPP Data Port 1
R/W DATA2. EPP Data Port 2
R/W DATA3. EPP Data Port 3
W CFIFO. PP Data FIFO
R/W DFIFO. ECP Data FIFO
R/W TFIFO. Test FIFO
RO CNFGA. Configuration A
RO CNFGB. Configuration B
R/W ECR. Extended Control
R/W EIR. Extended Index
R/W EDR. Extended Data
R/W EAR. Extended Auxiliary Status
Type Name
R/W Control0. Control Register 0
R/W Control2. Control Register 2
R/W Control4. Control Register 4
R/W PP Confg0. Parallel Port Configuration Register 0
5.8.1 Parallel Port
The Parallel Port supports all IEEE1284 standard commu-
nication modes: Compatibility (known also as Standard or
SPP), Bidirectional (known also as PS/2), FIFO, EPP
(known also as Mode 4) and ECP (with an optional
Extended ECP mode).
5.8.1.1 Parallel Port Register and Bit Maps
The Parallel Port register maps (Table 5-33 and Table 5-34)
are grouped according to first and second level offsets.
EPP and second level offset registers are available only
when the base address is 8-byte aligned.
Parallel Port functional block bit maps are shown in Table 5-
35 and Table 5-36.
32579B
Modes (ECR Bits) 7 6 5
000 or 001
011
All Modes
All Modes
100
100
100
100
100
010
011
110
111
111
All Modes
All Modes
All Modes
All Modes
129