AMD Geode SC1200 Data Book page 31

Signal Definitions
Table 3-2.
Ball I/O
No. Signal Name (PU/PD)
C1 AD26 I/O
D2 I/O
C2 AD24 I/O
D0 I/O
C3 V PWR
IO
C4 AD25 I/O
D1 I/O
C5 GNT0# O
DID0 I
(PD
100
C6 GNT1# O
DID1 I
(PD
100
C7 V PWR
IO
C8 ROMCS# O
BOOT16 I
(PD
100
C9 GPIO19 I/O
(PU
22.5
INTC# I
(PU
22.5
IOCHRDY I
(PU
22.5
C10 V PWR
IO
C11 IRTX O
SOUT3 O
C12 V GND
SSCRT
C13 AV PWR
CCCRT
C14 AV GND
SSCRT
C15 AV GND
SSCRT
C16 AV GND
SSPLL2
6,2 SLCT I
C17
TFTD15 O
F_C/BE3# O
C18 PD4 I/O
TFTD10 O
F_AD4 O
AMD Geode™ SC1200/SC1201 Processor Data Book
BGU481 Ball Assignment - Sorted by Ball Number (Continued)
1
Buffer Power
Type Rail Configuration
IN , V Cycle Multiplexed
PCI IO
O
PCI
IN ,
PCI
O
PCI
IN , V Cycle Multiplexed
PCI IO
O
PCI
IN ,
PCI
O
PCI
--- --- ---
IN , V Cycle Multiplexed
PCI IO
O
PCI
IN ,
PCI
O
PCI
O V ---
PCI IO
IN Strap (See Table 3-
STRP
) 4 on page 44.)
O V ---
PCI IO
IN Strap (See Table 3-
STRP
) 4 on page 44.)
--- --- ---
O V ---
3/5 IO
IN V Strap (See Table 3-
STRP IO
) 4 on page 44.)
IN , V PMR[9] = 0 and
TS IO
) PMR[4] = 0
O
3/5
IN PMR[9] = 0 and
TS
) PMR[4] = 1
IN PMR[9] = 1 and
TS1
) PMR[4] = 1
--- --- ---
O V PMR[6] = 0
8/8 IO
O PMR[6] = 1
8/8
--- --- ---
--- --- ---
--- --- ---
--- --- ---
--- --- ---
IN V 3
PMR[23] = 0 and
T IO
(PMR[27] = 0 and
FPCI_MON = 0)
O
3
PMR[23] = 1 and
1/4
(PMR[27] = 0 and
FPCI_MON = 0)
O 3
PMR[23] = 0 and
1/4
(PMR[27] = 1 or
FPCI_MON = 1)
IN , V 3
PMR[23] = 0 and
T IO
O
(PMR[27] = 0 and
14/14
FPCI_MON = 0)
O 3
PMR[23] = 1 and
1/4
(PMR[27] = 0 and
FPCI_MON = 0)
O 3
PMR[23] = 0 and
14/14
(PMR[27] = 1 or
FPCI_MON = 1)
Ball I/O
No. Signal Name (PU/PD)
6,2 PD5 I/O
C19
TFTD11 O
F_AD5 O
6,2 PD3 I/O
C20
TFTD9 O
F_AD3 O
6,2 PD0 I/O
C21
TFTD6 O
VOPD5 O
F_AD0 O
C22 V PWR
IO
C23 SVC O
Cr O
Cb O
TVB O
TVR O
C24 TVREF I/O
C25 V PWR
IO
C26 INTB# I
(PU
22.5
C27 AV GND
SSUSB
C28 GPIO9 I/O
(PU
22.5
DCD2# I
(PU
22.5
IDE_IOW1# O
(PU
22.5
SDTEST2 O
(PU
22.5
C29 V PWR
IO
32579B
1
Buffer Power
Type Rail Configuration
IN , V 3
PMR[23] = 0 and
T IO
O
(PMR[27] = 0 and
14/14
FPCI_MON = 0)
O 3
PMR[23] = 1 and
1/4
(PMR[27] = 0 and
FPCI_MON = 0)
O 3
PMR[23] = 0 and
14/14
(PMR[27] = 1 or
FPCI_MON = 1)
IN , V 3
PMR[23] = 0 and
T IO
O
(PMR[27] = 0 and
14/14
FPCI_MON = 0)
O 3
PMR[23] = 1 and
1/4
(PMR[27] = 0 and
FPCI_MON = 0)
O 3
PMR[23] = 0 and
14/14
(PMR[27] = 1 or
FPCI_MON = 1)
IN , V 3
PMR[23] = 0 and
T IO
O
(PMR[27] = 0 and
14/14
FPCI_MON = 0)
O 3
(PMR[23] = 1 and
1/4
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
O 3
(PMR[23] = 1 and
1/4
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
O 3
PMR[23] = 0 and
14/14
(PMR[27] = 1 or
FPCI_MON = 1)
--- --- ---
WIRE AV See F4BAR0+
CCTV
Memory Offset
C08h[4:3] bit
description on
page 356.
WIRE AV ---
CCTV
--- --- ---
IN V ---
PCI IO
)
--- --- ---
IN , V PMR[18] = 0 and
TS IO
) PMR[8] = 0
O
1/4
IN PMR[18] = 1 and
TS
) PMR[8] = 0
O PMR[18] = 0 and
1/4
) PMR[8] = 1
O PMR[18] = 1 and
2/5
) PMR[8] = 1
--- --- ---
31