Electrical Specifications
9.3.16
Power-Up Sequencing
Table 9-46. Power-Up Sequence Using the Power Button Timing Parameters
Symbol
Parameter
t
Voltage sequence
1
t
PWRBTN# inactive after V
2
applied, whichever is applied last
t
PWRBTN# active pulse width
3
t
ONCTL# inactive after V
4
t
Signal active after PWRBTN active
5
t
V
and V
6
CORE
active
t
POR# inactive after V
7
applied
V
SBL
V
SB
V
CORE
V
IO
PWRBTN#
ONTCL#
PWRCNT[2:1]
POR#
Figure 9-56. Power-Up Sequencing With PWRBTN# Timing Diagram
AMD Geode™ SC1200/SC1201 Processor Data Book
or V
SB
SBL
applied
SB
applied after ONCTL#
IO
and V
CORE
IO
t
1
t
2
t
4
Min
Max
Unit
-100
100
ms
0
1
µs
16
4000
ms
0
1
ms
14
16
ms
0
ms
50
ms
t
1
t
6
t
3
t
5
32579B
Comments
Optimum power-up results with
t
= 0.
1
PWRBTN# is an input and must
be powered by V
.
SB
If PWRBTN# max is exceeded,
ONCTL# will go inactive.
System determines when V
and V
are applied, hence there
IO
is no maximum constraint.
POR# must not glitch during
active time.
t
7
CORE
433
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