32579B
3.4.3
Video Port Interface Signals (Continued)
Signal Name
Ball No.
VOPD7
D20
VOPD6
A21
VOPD5
C21
VOPD4
B21
VOPD3
D21
VOPD2
B17
VOPD1
D22
VOPD0
A20
VOPCK
B18
3.4.4
CRT/TFT Interface Signals
Signal Name
Ball No.
DDC_SCL
Y1
DDC_SDA
Y2
HSYNC
A11
VSYNC
B11
VREF
D16
SETRES
B15
On-Chip RAMDAC
RED
B12
GREEN
A14
BLUE
A15
TFT (External DAC) Interface
52
Type
Description
O
Video Output Port Data. The data is output from the
Video Processor in VESA Video Interface Port Rev 1.1
Task B format.
O
Video Output Port Clock. The clock output from the
Video Processor.
Type
Description
O
DDC Serial Clock. This is the serial clock for the VESA
Display Data Channel interface. It is used for monitor
communications. The DDC2B standard is supported by
this interface.
I/O
DDC Serial Data. This is the bidirectional serial data sig-
nal for the VESA Display Data Channel interface. It is
used for monitor communications. The DDC2B standard
is supported by this interface.
O
Horizontal Sync
O
Vertical Sync
I/O
Voltage Reference. Reference voltage for CRT PLL and
DAC. This signal reflects the internal voltage reference. If
internal voltage reference is used (recommended), leave
this ball disconnected. If an external voltage reference is
used, this input is tied to a 1.235V reference.
I
Set Resistor. This signal sets the current level for the
RED/GREEN/BLUE analog outputs. Typically, a 464 Ω,
1% resistor is connected between this ball and AV
O
Analog Red, Green and Blue
.
SSCRT
AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Definitions
Mux
PD2+TFTD8+
F_AD2
PD1+TFTD7+
F_AD1
PD0+TFTD6+
F_AD0
INIT#+TFTD5+
SMI_O
ERR#+TFTD4+
F_CBE0#
BUSY/WAIT#+
TFTD3+F_C/BE1#
AFD#/DSTRB#+
TFTD2+INTR_O
PD6+TFTD1+
F_AD6
ACK#+TFTDE+
FPCICLK
Mux
IDE_DATA10
IDE_DATA9
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