Figure 9-8. Tft Timing Diagram; Table 9-15. Tft Timing Parameters - AMD Geode SC1200 Data Book

32579B
9.3.3 CRT and TFT Interface
Table 9-15 and Figure 9-8 describe the timing of the digital
CRT interface of the SC1200/SC1201 processor. All mea-
surement points in this table are identical to the voltage
measurement levels described in Table 9-11 on page 376.
Symbol Parameter
t TFTD[17:0], TFTDE valid time after
OV
TFTDCK rising edge (multiplexed on IDE)
t TFTD[17:0], TFTDE valid time after
OV
TFTDCK rising edge (multiplexed on
Parallel Port)
t TFTDCK rise/fall time between 0.8V and
CLK_RF
2.0V
t TFTDCK period time (multiplexed on IDE)
CLK_P
t TFTDCK period time (multiplexed on
CLK_P
Parallel Port)
t TFTDCK duty cycle
CLK_D
Note 1. Guaranteed by characterization.
TFTDCK
TFTD[17:0]
TFTDE
382
Note that signals DDC_SCL and DDC_SDA of the CRT
interface are compliant with standard ACCESS.bus timing
and are controlled by software.

Table 9-15. TFT Timing Parameters

Min
0
0
25
12.5
t
CLK_P
t
OV

Figure 9-8. TFT Timing Diagram

Max Unit
8 ns
4 ns
3 ns
ns
ns
40/60 %
t
CLK_RF
AMD Geode™ SC1200/SC1201 Processor Data Book
Electrical Specifications
Comments
Note 1