Figure 7-16. Pll Block Diagram - AMD Geode SC1200 Data Book

32579B
7.2.8 Integrated PLL
The integrated (CRT) PLL can generate frequencies up to
135 MHz from a single 27 MHz source. The clock fre-
quency is programmable using two registers. Figure 7-16
shows the block diagram of the Video Processor integrated
PLL.
F is 27 MHz, generated by an external crystal and an
REF
integrated oscillator. F is calculated from:
OUT
F = (m + 1) / (n+ 1) x F
OUT
n
F
REF
Divider
332
REF
Phase
Charge
Compare
m
Divider

Figure 7-16. PLL Block Diagram

The integrated PLL can generate any frequency by writing
into the CRT-m and CRT-n bit fields (FBAR0+Memory Off-
set 2Ch). Additionally, 16 preprogrammed VGA frequencies
can be selected via the PLL Clock Select register
(F4BAR0+Memory Offset 2Ch[19:16]), if the crystal oscilla-
tor has a frequency of 27 MHz. This PLL can be powered
down via the Miscellaneous register (F4BAR0+Memory
Offset 28h[12]).
Loop
Pump Filter
AMD Geode™ SC1200/SC1201 Processor Data Book
Video Processor Module
Out
VCO F
Divide
OUT