Figure 5-15. Access.bus Data Transaction; Figure 5-16. Access.bus Acknowledge Cycle - AMD Geode SC1200 Data Book

32579B
5.7.3 Acknowledge (ACK) Cycle
The ACK cycle consists of two signals: the ACK clock
pulse sent by the master with each byte transferred, and
the ACK signal sent by the receiving device (see Figure 5-
15).
The master generates the ACK clock pulse on the ninth
clock pulse of the byte transfer. The transmitter releases
ABD
ABC
Start
Condition
Data Output
by Transmitter
Data Output
by Receiver
ABC
122
MSB
2 3 - 6
1 7
S
Byte Complete
Interrupt Within
Receiver

Figure 5-15. ACCESS.bus Data Transaction

2 3 - 6
1
S
Start
Condition

Figure 5-16. ACCESS.bus Acknowledge Cycle

the ABD line (permits it to go high) to allow the receiver to
send the ACK signal. The receiver must pull down the ABD
line during the ACK clock pulse, signalling that it has cor-
rectly received the last data byte and is ready to receive
the next byte. Figure 5-16 illustrates the ACK cycle.
Acknowledge
Signal From Receiver
8
9 1 2 3 - 8
ACK
Clock Line Held
Low by Receiver
While Interrupt
is Serviced
Transmitter Stays Off Bus
During Acknowledge Clock
Acknowledge
Signal From Receiver
8
7 9
AMD Geode™ SC1200/SC1201 Processor Data Book
SuperI/O Module
9
P
ACK
Stop
Condition