Table 6-44. Dma - AMD Geode SC1200 Data Book

Signal Definitions
3.4.10 IDE Interface Signals
Signal Name Ball No.
IDE_RST# AA1
IDE_ADDR2 U2
IDE_ADDR1 AE1
IDE_ADDR0 AD3
IDE_DATA[15:0] See
Table 3-3
on page
40
IDE_IOR0# Y4
IDE_IOR1# D28
IDE_IOW0# AD2
IDE_IOW1# C28
IDE_CS0# AF2
IDE_CS1# P2
IDE_IORDY0 AD1
IDE_IORDY1 B29
IDE_DREQ0 AC4
IDE_DREQ1 C31
IDE_DACK0# AD4
IDE_DACK1# C30
IRQ14 AF1
IRQ15 AJ8
AMD Geode™ SC1200/SC1201 Processor Data Book
Type Description
O IDE Reset. This signal resets all devices attached to the
IDE interface.
O IDE Address Bits. These address bits are used to
access a register or data port in a device on the IDE bus.
I/O IDE Data Lines. IDE_DATA[15:0] transfers data to/from
the IDE devices.
O IDE I/O Read Channels 0 and 1. IDE_IOR0# is the read
signal for Channel 0 and IDE_IOR1# is the read signal
O
for Channel 1. Each signal is asserted at read accesses
to the corresponding IDE port addresses.
O IDE I/O Write Channels 0 and 1. IDE_IOW0# is the
write signal for Channel 0. IDE_IOW1# is the write signal
O
for Channel 1. Each signal is asserted at write accesses
to corresponding IDE port addresses.
O IDE Chip Selects 0 and 1. These signals are used to
select the command block registers in an IDE device.
O
I I/O Ready Channels 0 and 1. When de-asserted, these
signals extend the transfer cycle of any host register
I
access if the required device is not ready to respond to
the data transfer request.
Note: If selected as IDE_IORDY0 or IDE_IORDY1
function(s) but not used, then signal(s) should be
tied high.
I DMA Request Channels 0 and 1. The IDE_DREQ sig-
nals are used to request a DMA transfer from the
I
SC1200/SC1201 processor. The direction of transfer is
determined by the IDE_IOR/IOW signals.
Note: If selected as IDE_DREQ0/ IDE_DREQ1 func-
tion but not used, tie IDE_DREQ0/IDE_DREQ1
low.
O DMA Acknowledge Channels 0 and 1. The
IDE_DACK# signals acknowledge the DREQ request to
O
initiate DMA transfers.
I Interrupt Request Channels 0 and 1. These input sig-
nals are edge-sensitive interrupts that indicate when the
I
IDE device is requesting a CPU interrupt service.
Note: If selected as IRQ14/IRQ15 function but not
used, tie IRQ14/IRQ15 low.
32579B
Mux
TFTDCK
TFTD4
TFTD2
TFTD3
The IDE interface is
muxed with the TFT
interface. See Table
3-5 on page 45 for
muxing details.
TFTD10
GPIO6+DTR2#/
BOUT2+SDTEST5#
TFTD9
GPIO9+DCD2#+
SDTEST2
TFTD5
TFTDE
TFTD11
GPIO10+DSR2#+
SDTEST1
TFTD8
GPIO8+CTS2#
+SDTEST5
TFTD0
GPIO7+RTS2#
+SDTEST0
TFTD1
GPIO11+RI2#
61