Pci Bus Interface Signals - AMD Geode SC1200 Data Book

Signal Definitions
3.4.6 ACCESS.bus Interface Signals
Signal Name Ball No.
AB1C N31
AB1D N30
AB2C N29
AB2D M29
3.4.7

PCI Bus Interface Signals

Signal Name BalL No.
PCICLK A7
PCICLK0 A4
PCICLK1 D6
AD[31:24] See
Table 3-3
AD[23:0]
on page
40
C/BE3# H4
C/BE2# F3
C/BE1# J2
C/BE0# L1
AMD Geode™ SC1200/SC1201 Processor Data Book
Type Description
I/O ACCESS.bus 1 Serial Clock. This is the serial clock for
the interface.
Note: If selected as AB1C function but not used, tie
AB1C high.
I/O ACCESS.bus 1 Serial Data. This is the bidirectional
serial data signal for the interface.
Note: If AB1D function is selected but not used, tie
AB1D high.
I/O ACCESS.bus 2 Serial Clock. This is the serial clock for
the interface.
Note: If AB2C function is selected but not used, tie
AB2C high.
I/O ACCESS.bus 2 Serial Data. This is the bidirectional
serial data signal for the interface.
Note: If AB2D function is selected but not used, tie
AB2D high.
Type Description
I PCI Clock. PCICLK provides timing for all transactions
on the PCI bus. All other PCI signals are sampled on the
rising edge of PCICLK, and all timing parameters are
defined with respect to this edge.
O PCI Clock Outputs. PCICLK0 and PCICLK1 provide
clock drives for the system at 33 MHz. These clocks are
O
asynchronous to PCI signals. There is low skew between
all outputs. One of these clock signals should be con-
nected to the PCICLK input. All PCI clock users in the
system (including PCICLK) should receive the clock with
as low a skew as possible.
I/O Multiplexed Address and Data. A bus transaction con-
sists of an address phase in the cycle in which FRAME#
is asserted followed by one or more data phases. During
the address phase, AD[31:0] contain a physical 32-bit
address. For I/O, this is a byte address. For configuration
and memory, it is a DWORD address. During data
phases, AD[7:0] contain the least significant byte (LSB)
and AD[31:24] contain the most significant byte (MSB).
I/O Multiplexed Command and Byte Enables. During the
address phase of a transaction when FRAME# is active,
C/BE[3:0]# define the bus command. During the data
phase, C/BE[3:0]# are used as byte enables. The byte
enables are valid for the entire data phase and determine
which byte lanes carry meaningful data. C/BE0# applies
to byte 0 (LSB) and C/BE3# applies to byte 3 (MSB).
32579B
Mux
GPIO20+DOCCS#
GPIO1+IOCS1#
GPIO12
GPIO13
Mux
---
FPCI_MON (Strap)
LPC_ROM (Strap)
D[7:0]
A[23:0]
D11
D10
D9
D8
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