Memory Controller Interface; Figure 9-3. Memory Controller Drive Level And Measurement Points - AMD Geode SC1200 Data Book

Electrical Specifications
9.3.1

Memory Controller Interface

The minimum input setup and hold times described in Figure 9-3 (legend C and D) define the smallest acceptable sampling
window during which a synchronous input signal must be stable to ensure correct operation.
V
OH
SDCLK_OUT
SDCLK[3:0]
V
OL
V
OH
OUTPUTS
V
OL
V
IH
SDCLK_IN
V
IL
INPUTS
Legend: A = Maximum Output Delay
B = Minimum Output Delay
C = Minimum Input Setup
D = Minimum Input Hold

Figure 9-3. Memory Controller Drive Level and Measurement Points

AMD Geode™ SC1200/SC1201 Processor Data Book
V
OHD
V
OLD
B
Valid Output
n
V
IHD
V
ILD
V
IH
V
IL
t
x
A
Max
Min
Valid Output
t
x
C
32579B
V
REF
V
n+1 REF
V
REF
D
V
REF
377