Signal Definitions
Table 3-2.
Ball
I/O
No.
Signal Name
(PU/PD)
6, 2
AFD#/DSTRB#
O
D22
TFTD2
O
VOPD1
O
INTR_O
O
D23
AV
PWR
CCTV
D24
CVBS
O
Cr
O
TVB
O
D25
V
GND
SS
D26
INTA#
I
(PU
22.5
D27
AV
PWR
CCUSB
D28
GPIO6
I/O
(PU
22.5
DTR2#/BOUT2
O
(PU
22.5
IDE_IOR1#
O
(PU
22.5
SDTEST5
O
(PU
22.5
D29
SOUT2
O
CLKSEL2
I
(PD
100
D30
TDP
I/O
D31
TDN
I/O
E1
AD16
I/O
A16
O
E2
AD19
I/O
A19
O
E3
AD18
I/O
A18
O
E4
DEVSEL#
I/O
(PU
22.5
BHE#
O
E28
SIN2
I
SDTEST3
O
E29
TRST#
I
(PU
22.5
E30
TDO
O
E31
TCK
I
(PU
22.5
AMD Geode™ SC1200/SC1201 Processor Data Book
BGU481 Ball Assignment - Sorted by Ball Number (Continued)
1
Buffer
Power
Type
Rail
Configuration
O
V
3
PMR[23]
= 0 and
14/14
IO
(PMR[27] = 0 and
FPCI_MON = 0)
O
3
PMR[23]
= 1 and
1/4
PMR[15] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
O
3
(PMR[23]
= 1 and
1/4
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
O
3
PMR[23]
= 0 and
14/14
(PMR[27] = 1 or
FPCI_MON = 1)
---
---
---
WIRE
AV
See F4BAR0+
CCTV
Memory Offset
C08h[4:3] bit
description on
page 356.
---
---
---
IN
V
---
PCI
IO
)
---
---
---
IN
,
V
PMR[18] = 0 and
TS
IO
)
PMR[8] = 0
O
1/4
O
PMR[18] = 1 and
1/4
)
PMR[8] = 0
O
PMR[18] = 0 and
1/4
)
PMR[8] = 1
O
PMR[18] = 1 and
2/5
)
PMR[8] = 1
O
V
---
8/8
IO
IN
Strap (See Table 3-
STRP
)
4 on page 44.)
Diode
---
---
WIRE
V
---
IO
IN
,
V
Cycle Multiplexed
PCI
IO
O
PCI
O
PCI
IN
,
V
Cycle Multiplexed
PCI
IO
O
PCI
O
PCI
IN
,
V
Cycle Multiplexed
PCI
IO
O
PCI
O
PCI
IN
,
V
Cycle Multiplexed
PCI
IO
)
O
PCI
O
PCI
IN
V
PMR[28] = 0
TS
IO
O
PMR[28] = 1
2/5
IN
V
---
PCI
IO
)
O
V
---
PCI
IO
IN
V
---
PCI
IO
)
Ball
I/O
No.
Signal Name
(PU/PD)
F1
TRDY#
I/O
(PU
22.5
D13
I/O
(PU
22.5
F2
IRDY#
I/O
(PU
22.5
D14
I/O
(PU
22.5
F3
C/BE2#
I/O
(PU
22.5
D10
I/O
(PU
22.5
F4
AD17
I/O
A17
O
F28
TMS
I
(PU
22.5
F29
TDI
I
(PU
22.5
F30
GTEST
I
(PD
22.5
F31
VPCKIN
I
G1
STOP#
I/O
(PU
22.5
D15
I/O
(PU
22.5
G2
V
GND
SS
G3
V
PWR
IO
G4
V
GND
SS
G28
V
GND
SS
G29
V
PWR
IO
G30
V
GND
SS
G31
VPD7
I
H1
SERR#
I/O
(PU
22.5
H2
PERR#
I/O
(PU
22.5
H3
LOCK#
I/O
(PU
22.5
H4
C/BE3#
I/O
(PU
22.5
D11
I/O
(PU
22.5
H28
VPD6
I
H29
VPD5
I
H30
VPD4
I
H31
VPD3
I
J1
AD13
I/O
A13
O
32579B
1
Buffer
Power
Type
Rail
Configuration
IN
,
V
Cycle Multiplexed
PCI
IO
)
O
PCI
IN
,
PCI
)
O
PCI
IN
,
V
Cycle Multiplexed
PCI
IO
)
O
PCI
IN
,
PCI
)
O
PCI
IN
,
V
Cycle Multiplexed
PCI
IO
)
O
PCI
IN
,
PCI
)
O
PCI
IN
,
V
Cycle Multiplexed
PCI
IO
O
PCI
O
PCI
IN
V
---
PCI
IO
)
IN
V
---
PCI
IO
)
IN
V
---
T
IO
)
IN
V
---
T
IO
IN
,
V
Cycle Multiplexed
PCI
IO
)
O
PCI
IN
,
PCI
)
O
PCI
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
IN
V
---
T
IO
IN
,
V
---
PCI
IO
)
OD
PCI
IN
,
V
---
PCI
IO
)
O
PCI
IN
,
V
---
PCI
IO
)
O
PCI
IN
,
V
Cycle Multiplexed
PCI
IO
)
O
PCI
IN
,
PCI
)
O
PCI
IN
V
---
T
IO
IN
V
---
T
IO
IN
V
---
T
IO
IN
V
---
T
IO
IN
,
V
Cycle Multiplexed
PCI
IO
O
PCI
O
PCI
33
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