SuperI/O Module
Register
Offset
Name
00h
RXD
TXD
01h
1
IER
2
IER
02h
1
EIR
2
EIR
FCR
03h
5
LCR
5
BSR
04h
1
MCR
2
MCR
05h
LSR
ER_INF
06h
MSR
07h
1
SPR
2
ASCR
1.
Non-Extended Mode.
2.
Extended Mode.
3.
In SP1 only.
4.
In SP2 only.
5.
When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-38 on page 132.
Register
Offset
Name
00h
LBGD(L)
01h
LBGD(H)
02h
RSVD
03h
1
LCR
1
BSR
04h-07h
RSVD
1.
When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-38 on page 132.
AMD Geode™ SC1200/SC1201 Processor Data Book
Table 5-42. Bank 0 Bit Map
7
6
RSVD
RSVD
TXEMP_IE
FEN[1:0]
RSVD
TXEMP_EV
RXFTH[1:0]
BKSE
SBRK
STKP
BKSE
RSVD
RSVD
TXEMP
TXRDY
DCD
RI
DSR
RSVD
4
TXUR
RXACT
Table 5-43. Bank 1 Bit Map
7
6
BKSE
SBRK
STKP
BKSE
Bits
5
4
3
RXD[7:0] (Receiver Data Bits)
TXD[7:0] (Transmitter Data Bits)
MS_IE
3
MS_IE
RSVD
/
4
DMA_IE
RSVD
RXFT
3
MS_EV
RSVD
/
4
DMA_EV
TXFTH[1:0]
RSVD
EPS
PEN
BSR[6:0] (Bank Select)
LOOP
ISEN or
DCDLP
TX_DFR
BRK
FE
CTS
DDCD
Scratch Data
4
4
RSVD
RXWDG
Bits
5
4
3
LBGD[7:0] (Low Byte)
LBGD[15:8] (High Byte)
Reserved
EPS
PEN
BSR[6:0] (Bank Select)
Reserved
32579B
2
1
LS_IE
TXLDL_IE
RXHDL_IE
LS_IE
TXLDL_IE
RXHDL_IE
IPR1
IPR0
LS_EV or
TXLDL_EV RXHDL_EV
TXHLT_EV
TXSR
RXSR
FIFO_EN
STB
WLS[1:0]
RILP
RTS
RSVD
RTS
PE
OE
TERI
DDSR
4
RSVD
RXF_TOUT
S_OET
2
1
STB
WLS[1:0]
0
IPF
DTR
DTR
RXDA
DCTS
0
133
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