Figure 9-25. Register Transfer To/From Device Timing Diagram - AMD Geode SC1200 Data Book

Electrical Specifications
1
ADDR valid
IDE_IOR0#
IDE_IOW0#
WRITE
IDE_DATA[7:0]
READ
IDE_DATA[7:0]
2,3
IDE_IORDY0
2,4
IDE_IORDY0
2,5
IDE_IORDY0
Notes:
1) Device address consists of signals IDE_CS[0:1]# and IDE_ADDR[2:0].
2) Negation of IDE_IORDY0,1 is used to extend the PIO cycle. The determination of whether or not the cycle is to be
extended is made by the host after t
3) Device never negates IDE_IORDY[0:1]. Device keeps IDE_IORDY[0:1] released, and no wait is generated.
4) Device negates IDE_IORDY[0:1] before t
released, and no wait is generated.
5) Device negates IDE_IORDY[0:1] before t
more than 5 ns before release. A wait is generated.
6) The cycle completes after IDE_IORDY[0:1] is reasserted. For cycles where a wait is generated and IDE_IOR[0:1] is
asserted, the device places read data on IDE_DATA[15:0] for t

Figure 9-25. Register Transfer to/from Device Timing Diagram

AMD Geode™ SC1200/SC1201 Processor Data Book
t
0
t
t
1
2
t
A
t
C
from the assertion of IDE_IOR[0:1]# or IDE_IOW[0:1]#.
A
but causes IDE_IORDY[0:1] to be asserted before t
A
. IDE_IORDY[0:1] is released prior to negation and may be asserted for no
A
RD
32579B
t
9
t
2i
t
3
t
4
t
5
t
6
t
6z
t
RD
t
t
B
C
before asserting IDE_IORDY[0:1].
. IDE_IORDY[0:1] is
A
401