Spi Control Interface - Xilinx MIcroBlaze Development Spartan-3E 1600E Kit User Manual

Chapter 10: Analog Capture Circuit
Table 10-2: Programmable Gain Settings for Pre-Amplifier (Continued)

SPI Control Interface

Figure 10-3
for each amplifier is sent as an 8-bit command word, consisting of two 4-bit fields. The
most-significant bit, B3, is sent first.
The AMP_DOUT output from the amplifier echoes the previous gain settings. These
values can be ignored for most applications.
The SPI bus transaction starts when the FPGA asserts AMP_CS Low (see
amplifier captures serial data on SPI_MOSI on the rising edge of the SPI_SCK clock signal.
The amplifier presents serial data on AMP_DOUT on the falling edge of SPI_SCK.
The amplifier interface is relatively slow, supporting only about a 10 MHz clock frequency.
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A3
Gain
B3
-50 0
-100 0
highlights the SPI-based communications interface with the amplifier. The gain
Spartan-3E
FPGA
Master
Figure 10-3: SPI Serial Interface to Amplifier
AMP_CS
30
SPI_SCK
SPI_MOSI
7
(from FPGA)
AMP_DOUT
Previous 7
(from AMP)
All timing is minimum in nanoseconds unless otherwise noted.
Figure 10-4: SPI Timing When Communicating with Amplifier
A2 A1
B2 B1
1 1
1 1
AMP_DOUT
Slave: LTC2624-1
0
SPI_MOSI
A A A
0 1 2
AMP_CS
SPI_SCK
A Gain
50
30
6 5
85 max
MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
A0 Input Voltage Range
B0 Minimum
0 1.625
1 1.6375
7
A B B B B
3 0 1 2 3
B Gain
UG257_10_03_060706
Figure
50
4 3 2
UG257 (v1.1) December 5, 2007
R
Maximum
1.675
1.6625
10-4). The
UG570_10_04_060706