Xilinx MIcroBlaze Development Spartan-3E 1600E Kit User Manual page 88

Chapter 11: Intel StrataFlash Parallel NOR Flash PROM
Table 11-1: FPGA-to-StrataFlash Connections
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StrataFlash
Category Signal Name
SF_D15
SF_D14
SF_D13
SF_D12
SF_D11
SF_D10
SF_D9
SF_D8
SF_D7
SF_D6
SF_D5
SF_D4
SF_D3
SF_D2
SF_D1
SPI_MISO
SF_CE0
SF_WE
SF_OE
SF_BYTE
SF_STS
FPGA Pin
Number
T8 Upper 8 bits of a 16-bit
halfword when
R8
StrataFlash is
P6
configured for x16
data
M16
(SF_BYTE=High).
M15
Connects to FPGA
user I/O.
P17
R16
R15
N9 Upper 7 bits of a data byte or lower 8 bits of a
16-bit halfword. Connects to FPGA pins D[7:1]
M9
to support the BPI configuration.
R9
U9
V9
R10
P10
N10 Bit 0 of data byte and 16-bit halfword.
Connects to FPGA pin D0/DIN to support the
BPI configuration. Shared with other SPI
peripherals and Platform Flash PROM.
D16 StrataFlash Chip Enable. Connects to FPGA
pin LDC0 to support the BPI configuration.
D17 StrataFlash Write Enable. Connects to FPGA
pin HDC to support the BPI configuration.
C18 StrataFlash Chip Enable. Connects to FPGA
pin LDC1 to support the BPI configuration.
C17 StrataFlash Byte Enable. Connects to FPGA pin
LDC2 to support the BPI configuration.
0: x8 data
1: x16 data
B18 StrataFlash Status signal. Connects to FPGA
user-I/O pin.
MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
Function
Signals SF_D<15:8>
connect to character
LCD pins DB[7:0].
UG257 (v1.1) December 5, 2007
R