Ddr Sdram Connections - Xilinx MIcroBlaze Development Spartan-3E 1600E Kit User Manual

Chapter 13: DDR SDRAM
The differential clock pin SD_CK_P is fed back into FPGA pin B9 in I/O Bank 0 to have best
access to one of the FPGA's Digital Clock Managers (DCMs). This path is required when
using the MicroBlaze OPB DDR controller. The MicroBlaze OPB DDR SDRAM controller
IP core documentation is also available from within the EDK 8.1i development software
(see

DDR SDRAM Connections

Table 13-1
Table 13-1: FPGA-to-DDR SDRAM Connections
106
www.xilinx.com
"Related Resources," page
shows the connections between the FPGA and the DDR SDRAM.
DDR SDRAM
Category Signal Name
SD_A12
SD_A11
SD_A10
SD_A9
SD_A8
SD_A7
SD_A6
SD_A5
SD_A4
SD_A3
SD_A2
SD_A1
SD_A0
109).
FPGA Pin
Number
P2 Address inputs
N5
T2
N4
H2
H1
H3
H4
E4
P1
R2
R3
T1
MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
Function
UG257 (v1.1) December 5, 2007
R