Programmable Pre-Amplifier; Interface; Programmable Gain - Xilinx MIcroBlaze Development Spartan-3E 1600E Kit User Manual

R
The reference design files provide more information on converting the voltage applied on
VINA or VINB to a digital representation (see

Programmable Pre-Amplifier

The LTC6912-1 provides two independent inverting amplifiers with programmable gain.
The purpose of the amplifier is to scale the incoming voltage on VINA or VINB so that it
maximizes the conversion range of the DAC, namely 1.65 1.25V.

Interface

Table 10-1
SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The
AMP_CS signal is the active-Low slave select input to the amplifier.
Table 10-1: AMP Interface Signals

Programmable Gain

Each analog channel has an associated programmable gain amplifier (see
Analog signals presented on the VINA or VINB inputs on header J7 are amplified relative
to 1.65V. The 1.65V reference is generated using a voltage divider of the 3.3V voltage
supply.
The gain of each amplifier is programmable from -1 to -100, as shown in
Table 10-2: Programmable Gain Settings for Pre-Amplifier
MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
UG257 (v1.1) December 5, 2007
lists the interface signals between the FPGA and the amplifier. The SPI_MOSI,
Signal FPGA Pin
SPI_MOSI T4
AMP_CS N7
SPI_SCK U16
AMP_SHDN P7
AMP_DOUT E18
A3
Gain
B3
0 0
-1 0
-2 0
-5 0
-10 0
-20 0
"Related Resources," page
Direction
FPGA AD Serial data: Master Output, Slave Input.
Presents 8-bit programmable gain settings, as
defined in
FPGA AMP Active-Low chip-select. The amplifier gain is
set when signal returns High.
FPGA AMP Clock
FPGA AMP Active-High shutdown, reset
FPGA AMP Serial data. Echoes previous amplifier gain
settings. Can be ignored in most applications.
A2 A1
B2 B1
0 0
0 0
0 1
0 1
1 0
1 0
Programmable Pre-Amplifier
81).
Description
Table 10-2.
Figure 10-2).
Table 10-2.
A0 Input Voltage Range
B0 Minimum Maximum
0
1 0.4
0 1.025 2.275
1 1.4
0 1.525 1.775
1 1.5875 1.7125
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