Location; Clock Period Constraints; Related Resources - Xilinx MIcroBlaze Development Spartan-3E 1600E Kit User Manual

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Location

Figure 3-2
I/O pin assignment and the I/O standard used. The settings assume that jumper JP9 is set
for 3.3V. If JP9 is set for 2.5V, adjust the IOSTANDARD settings accordingly.

Clock Period Constraints

The Xilinx ISE development software uses timing-driven logic placement and routing. Set
the clock PERIOD constraint as appropriate. An example constraint appears in
for the on-board 50 MHz clock oscillator. The CLK_50MHZ frequency is 50 MHz, which
equates to a 20 ns period. The output duty cycle from the oscillator ranges between 40% to
60%.

Related Resources

MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
UG257 (v1.1) December 5, 2007
provides the UCF constraints for the three clock input sources, including the
NET "CLK_50MHZ" LOC = "C9"
NET "CLK_SMA"
NET "CLK_AUX"
Figure 3-2: UCF Location Constraints for Clock Sources
# Define clock period for 50 MHz oscillator
NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;
Figure 3-3: UCF Clock PERIOD Constraint
Epson SG-8002JF Series Oscillator Data Sheet (50 MHz Oscillator)
http://www.eea.epson.com/go/Prod_Admin/Categories/EEA/QD/Crystal_Oscillators/
prog_oscillators/go/Resources/TestC2/SG8002JF
| IOSTANDARD = LVCMOS33 ;
LOC = "A10" | IOSTANDARD = LVCMOS33 ;
LOC = "B8" | IOSTANDARD = LVCMOS33 ;
Related Resources
UG257_03_02_061306
Figure 3-3
UG257_03_03_060206
www.xilinx.com
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