Ucf Location Constraints - Xilinx MIcroBlaze Development Spartan-3E 1600E Kit User Manual
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Chapter 10: Analog Capture Circuit
AD_CONV
Figure 10-7
SPI slave select enable. Be sure to provide enough SPI_SCK clock cycles so that the ADC
leaves the SPI_MISO signal in the high-impedance state. Otherwise, the ADC blocks
communication to the other SPI peripherals. As shown in
communications sequence. The ADC 3-states its data output for two clock cycles before
and after each 14-bit data transfer.
AD_CONV
SPI_MISO
UCF Location Constraints
Figure 10-8
including the I/O pin assignment and I/O standard used.
80
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SPI_MISO
6
6
6
6
0
1
2
3
AD_CONV
Z
SPI_SCK
Converted data is presented with a latency of one sample.
The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD_CONV.
The converted values is then presented after the next AD_CONV pulse.
Sample point
SPI_SCK
Channel 0
SPI_MISO
13
Figure 10-6: Analog-to-Digital Conversion Interface
shows detailed transaction timing. The AD_CONV signal is not a traditional
4ns min
3ns
SPI_SCK
1
High-Z
AD_CONV
30
SPI_SCK
Channel 1
SPI_MISO
3
The A/D converter sets its SDO output line to high impedance after 33 SPI_SCK clock cycles
Figure 10-7: Detailed SPI Timing to ADC
provides the User Constraint File (UCF) constraints for the amplifier interface,
Slave: LTC1407A-1 A/D Converter
6
6
6
6
6
6
6
6
6
6
4
5
6
7
8
9
10
11
12
13
Z
Channel 1
Channel 1
0
13
2
3
Channel 0
13
31
32
2
1
MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
6
6
6
6
6
6
6
6
6
6
6
0
1
2
3
4
5
6
7
8
9
10
Channel 0
Sample point
0
UG257_10_06_060706
Figure
10-6, use a 34-cycle
19.6ns min
4
5
8ns
12
11
45ns min
33
34
6ns
High-Z
0
UG257 (v1.1) December 5, 2007
R
6
6
6
11
12
13
Z
Channel 0
13
6
UG257_10_07_060706
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