Spi Communication Details; Communication Protocol - Xilinx MIcroBlaze Development Spartan-3E 1600E Kit User Manual

R
Although the StrataFlash PROM is a parallel device, its least-significant data bit is shared
with the SPI_MISO signal.
Table 9-2: Disabled Devices on the SPI Bus

SPI Communication Details

Figure 9-3
received relative to the SPI_SCK clock signal. The bus is fully static and supports clocks
rate up to the maximum of 50 MHz. However, check all timing parameters using the
LTC2624 data sheet if operating at or close to the maximum speed.
After driving the DAC_CS slave select signal Low, the FPGA transmits data on the
SPI_MOSI signal, MSB first. The LTC2624 captures input data (SPI_MOSI) on the rising
edge of SPI_SCK; the data must be valid for at least 4 ns relative to the rising clock edge.
The LTC2624 DAC transmits its data on the SPI_MISO signal on the falling edge of
SPI_SCK. The FPGA captures this data on the next rising SPI_SCK edge. The FPGA must
read the first SPI_MISO value on the first rising SPI_SCK edge after DAC_CS goes Low.
Otherwise, bit 31 is missed.
After transmitting all 32 data bits, the FPGA completes the SPI bus transaction by
returning the DAC_CS slave select signal High. The High-going edge starts the actual
digital-to-analog conversion process within the DAC.

Communication Protocol

Figure 9-4
DAC. The DAC supports both a 24-bit and 32-bit protocol. The 32-bit protocol is shown.
Inside the D/A converter, the SPI interface is formed by a 32-bit shift register. Each 32-bit
command word consists of a command, an address, followed by data value. As a new
command enters the DAC, the previous 32-bit command word is echoed back to the
MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
UG257 (v1.1) December 5, 2007
Signal
SPI_SS_B SPI serial Flash
AMP_CS Programmable pre-amplifier
AD_CONV Analog-to-Digital Converter (ADC)
SF_CE0 StrataFlash Parallel Flash PROM
FPGA_INIT_B Platform Flash PROM
shows a detailed example of the SPI bus timing. Each bit is transmitted or
DAC_CS
SPI_MOSI
SPI_SCK
SPI_MISO
Figure 9-3: SPI Communication Waveforms
shows the communications protocol required to interface with the LTC2624
Disabled Device
31 30
Previous 31 Previous 30
SPI Communication
Disable Value
1
1
0
1
1
29
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