Xilinx MIcroBlaze Development Spartan-3E 1600E Kit User Manual page 121

R
Spartan-3E data sheet. Select pairs have optional landing pads for external termination
resistors.
These signals are not routed with matched differential impedance, as would be required
for ultimate performance. However, all traces have similar lengths to minimize skew.
Table 15-2: Differential I/O Pairs
Differential
MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
UG257 (v1.1) December 5, 2007
Signal FPGA
Pair Name Pins
FX2_IO1 B4
1
FX2_IO2 A4
FX2_IO3 D5
2
FX2_IO4 C5
FX2_IO5 A6
3
FX2_IO6 B6
FX2_IO7 E7
4
FX2_IO8 F7
FX2_IO9 D7
5
FX2_IO10 C7
FX2_IO11 F8
6
FX2_IO12 E8
FX2_IO13 F9
7
FX2_IO14 E9
FX2_IO15 D11
8
FX2_IO16 C11
FX2_IO17 F11
9
FX2_IO18 E11
FX2_IO19 E12
10
FX2_IO20 F12
FX2_IO21 A13
11
FX2_IO22 B13
FX2_IO23 A14
12
FX2_IO24 B14
FX2_IO25 C14
13
FX2_IO26 D14
FX2_IO27 A16
14
FX2_IO28 B16
Hirose 100-pin FX2 Edge Connector (J3)
FPGA Pin Name Direction DIFF_TERM
IO_L24N_0 I/O
IO_L24P_0 I/O
IO_L23N_0 I/O
IO_L23P_0 I/O
IO_L20N_0 I/O
IO_L20P_0 I/O
IO_L19N_0 I/O
IO_L19P_0 I/O
IO_L18N_0 I/O
IO_L18P_0 I/O
IO_L17N_0 I/O
IO_L17P_0 I/O
IP_L15N_0 I/O
IP_L15P_0 I/O
IP_L09N_0 I/O
IP_L09P_0 I/O
IO_L08N_0 I/O
IO_L08P_0 I/O
IO_L06N_0 I/O
IO_L06P_0 I/O
IO_L05P_0 I/O
IO_L05N_0 I/O
IO_L04N_0 I/O
IO_L04P_0 I/O
IO_L03N_0 I/O
IO_L03P_0 I/O
IO_L01N_0 I/O
IO_L01P_0 I/O
External
Resistor
Designator
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
R202
Yes
Yes
R203
Yes
Yes
R204
Yes
Yes
R205
Yes
Yes
R206
Yes
Yes
R207
Yes
119
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