Ucf Location Constraints - Xilinx MIcroBlaze Development Spartan-3E 1600E Kit User Manual

Chapter 16: XC2C64A CoolRunner-II CPLD
JP10
WDT_EN
Spartan-3E FPGA
PROG_B
Figure 16-1: XC2C64A CoolRunner-II CPLD Controls Master Serial and BPI Configuration Modes

UCF Location Constraints

There are two sets of constraints listed below
XC2C64A CoolRunner-II CPLD.
128
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3.3V
XC_WDT_EN
XC_CMD<1>
(N18)
XC_CMD<0>
(P18)
XC_D<2>
(F17)
XC_D<1>
(F18)
XC_D<0>
(G16)
FPGA_M2
(T10)
FPGA_M1
(V11)
FPGA_M0
(M10)
XC_CPLD_EN
(D10)
XC_TRIG
(R17)
XC_DONE
DONE
XC_PROG_B
XC_GCK0
(H16)
GCLK10
(C9)
SPI_SCK
(U16)
(FX2_IO<32>)
SF_A<24>
(A11)
SF_A<23>
(N11)
SF_A<22>
(V12)
SF_A<21>
(V13)
SF_A<20>
(T12)
A[23:20]
A[19:0]
A[23:20] Unconnected
XC2C64A VQ44
CoolRunner-II CPLD
(P16)
(P30)
(P29)
(P36)
(P34)
(P33)
(P8)
XC_PF_CE
(P6) (P2)
(P5)
(P42)
(P41)
(P40)
(P39)
(P43)
(P1)
(P44)
(P23)
(P22)
(P21)
(P20)
(P19)
SF_A<19:0>
–
one for the Spartan-3E FPGA and one for the
MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
Required for Master Serial Mode
E nable Platform Flash PROM when
M[2:0]=000
XCF04S
Platform Flash PROM
CE
During Configuration:
BPI Up: A[24:20]=00000
BPI Down: A[24:20]=11111
After Configuration or Other Modes:
A[24:20]=ZZZZ
Intel StrataFlash
A[24:20]
A[19:0]
UG257 (v1.1) December 5, 2007
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