Part 3.3: Spi Flash - Xilinx AV6045 User Manual

DDR3 is connected to the BANK3 of the FPGA.
DDR3 Pin Assignment
Pin Name
DDR3_A[0]
DDR3_A[1]
DDR3_A[2]
DDR3_A[3]
DDR3_A[4]
DDR3_A[5]
DDR3_A[6]
DDR3_A[7]
DDR3_A[8]
DDR3_A[9]
DDR3_A[10]
DDR3_nRAS
DDR3_nWE
DDR3_ODT
DDR3_RESET
DDR3_LDM
DDR3_UDM
DDR3_DQ[0]
DDR3_DQ[1]
DDR3_DQ[2]
DDR3_DQ[3]
DDR3_DQ[4]
DDR3_DQ[5]
DDR3_DQ[6]
DDR3_DQ[7]

Part 3.3: SPI Flash

The FPGA core board AC6045 is equipped with one 64MBit SPI FLASH,
and the model is W25Q64BV, which uses the 3.3V CMOS voltage standard.
15 / 54
FPGA Video Processing Development Platform AV6045 User Manual
FPGA Pin
H2
H1
H5
K6
F3
K3
J4
H6
E3
E1
G4
K5
F2
J6
C3
L4
M3
N3
N1
M2
M1
J3
J1
K2
K1
Contact Email: rachel.zhou@alinx.com.cn
Pin Name
DDR3_A[11]
DDR3_A[12]
DDR3_A[13]
DDR3_A[14]
DDR3_BA[0]
DDR3_BA[1]
DDR3_BA[2]
DDR3_nCAS
DDR3_CKE
DDR3_CLK_P
DDR3_CLK_N
DDR3_DQ[8]
DDR3_DQ[9]
DDR3_DQ[10]
DDR3_DQ[11]
DDR3_DQ[12]
DDR3_DQ[13]
DDR3_DQ[14]
DDR3_DQ[15]
DDR3_LDQS_P
DDR3_LDQS_N
DDR3_UDQS_P
DDR3_UDQS_N
FPGA Pin
C1
D1
G6
F5
G3
G1
F1
K4
D2
H4
H3
P2
P1
R3
R1
U3
U1
V2
V1
L3
L1
T2
T1